Software Verification and Debug in the MPSoC Era

The eventual solution will be a paradigm shift in the abstraction on the software side " much like hardware design moved from gates to RTL. Once software design switches from sequential to parallel design entry, tools for targeting parallel software to parallel hardware with "correct by construction" flows will begin to emerge. Yet in the path to this new way of designing software/hardware systems, designers will face legacy software on complex multiprocessor systems on chip (MPSoC).
This will be compounded as the verification of sequential software has never been an easy task, but the challenges of software parallelism and multiple processors will make software verification more difficult. As a result a new breed of programming and debug solutions will be required, helping programmers to deal with the specific software verification challenges in MPSoCs.

The Challenge " Parallel Software in Parallel Hardware
Consider an application as outlined in Figure 1. It shows a typical streaming application with a set of video scaler algorithms dealing with two video channels, displaying the results of one as "Picture in Picture" (PIP) in the other.

1. This is an example of streaming application.

Each of the incoming channels has been H.264 decoded, is then scaled, one line is filtered and then they are mixed for display. In addition a still picture is overlaid in the mixer to the right. When mapped to real hardware all of this has to execute within the time it takes to display a picture to meet decoding deadlines. Overall this application has 13 unique tasks which could be executed in parallel and 33 communications between the tasks.
When implementing this application on an MPSoC, different options of hardware implementation may be available. A fairly generic MPSoC is shown in Figure 2 along with a potential allocation of the different application tasks to the processors.

2. A generic MPSoC platform is shown here.

This platform has four CPUs with their own individual memories, interacting with each other via a shared bus system and a shared memory. A couple of dedicated hardware peripherals are available for video in and output as well as user interaction via keys and on screen display (OSD). This platform can be homogeneous or heterogeneous, i.e. often MPSoCs provide a control processor and a dedicated set of processor for the multimedia streaming. In addition several mechanisms of communication are typically available, from shared busses to dedicated DMA controllers and even dedicated FIFO based communications between different domains of the MPSoC.
The challenge now lies in mapping the application as software tasks running on the processors predictably and in an optimized fashion. In a traditional flow the software developer will decide for each of the tasks which processor to map it to, manually instantiate all the communications between the different tasks, use the compiler specific tool chains and manually generate software images representing the set of tasks for each of the processors.

Page 2: MP Debug is Hard
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