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Synopsys' Synphony High Level Synthesis product purports to increase design and verification productivity up to 10 times higher than traditional RTL flows for communications and multimedia applications.
According to the announcement last week Synphony HLS creates optimized RTL for both ASIC and FPGA implementation, architecture exploration and rapid prototyping.
Harry the ASIC Guy took a gander at the product in his blog.
Harry Gries, ASIC Methodology and EDA Technology Consultant, has ten reasons why he is both excited and disappointed in the announcement.
The discussion following the blog post, instead of arguing Gries' technical evaluation, for the most part homes in on that the company "embargoed" the announcement, — a recipe for feeding and controlling the news about the new product.
Even in the age of the Internet, when discussions are for free, a technical community of EDA tool users prefers to evaluate products on their own, in the cubbyholes of their daily grind.
No time for idle chatter about "embargoes".
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