LONDON — A Serial RapidIO 2.1 endpoint soft IP core for the Lattice ECP3 FPGA family has been developed by Praesum Communications (Petaluma, Calif.). Lattice Semiconductor Corp. has licensed this IP core from Praesum and has full rights to use and sub-license it.
The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry.
The combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA will allow customers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost. The Serial RapidIO 2.1 core together other Lattice IP cores such as low latency CPRI and GbE/SGMII comprise a comprehensive IP suite in support of wireless infrastructure applications.
"We are pleased to have been selected to provide RapidIO 2.1 endpoint IP for the Lattice low cost ECP3 FPGA," said Kent Dahlgren, Praesum's CEO. "As the only supplier of fully compliant RapidIO 2.1 IP, Praesum's partnership with Lattice will help to accelerate deployment of this next generation technology in high performance signal processing applications. When combined with our RapidIO 2.1 switching IP, the endpoint IP for the LatticeECP3 FPGA represents a complete solution for wireless infrastructure equipment vendors."
Praesum's small footprint Serial RapidIO 2.1 IP core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces.
The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are suitable for high performance RF, baseband and image signal processing.
Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
