Looking for opportunities

For many years the ITRS has correctly predicted the adoption by the majority of design houses of semiconductor fabrication nodes. And with every step on the predicted, if not dictated, path, the EDA industry has found its challenges and its opportunities. But a funny thing is happening, now that we have entered the era of very deep sub-micron process. The majority of design houses are not moving to the most advanced fabrication node as swiftly as in the past.

It is true that there are still a couple of dozen companies that need to be at the leading edge of semiconductor capabilities in order to compete successfully, Intel, AMD, and Nvidia being the most representative. It is also clear that FPGA companies, like Xilinx and Altera, see the most advanced node as an opportunity to increase capacity, lower power requirements, and improve their competitive position against ASIC devices. But in spite of their considerable purchasing power, these companies alone will not keep the EDA industry viable.

Since tools that address the most advanced processing node are also the most profitable, EDA vendors are seeing the pool of providers of high margin revenue evaporating to a puddle. It is also true that the creation of new EDA companies has been centered around the need to provide evolutionary, and in some cases, revolutionary, solutions to the latest design and fabrication problems presented by a new process node. With fewer potential customers, the number of startups is bound to decline and their potential to reach a viable level of revenue is also going to be lower. This significantly impacts the probability of a new stock public offerings by EDA companies, and even significant acquisitions of startups by the four largest companies, who will find themselves strapped for cash. The disappointing revenue news from Cadence is just the latest, and most visible, indicator that a new business model is urgently needed.

The opportunities
Historically most EDA standards have been developed by four organizations: the IEEE, Accellera, Si2, and OSCI. The IEEE has been the leader, both in terms of numbers and international visibility, followed by the other three, in the order I wrote them. Many of the standards developed by Accellera have gone on to become IEEE standards, and OSCI has adopted the same process, although its mission is much more restrictive than Accellera. Si2 has preferred to form industrial coalitions, from which it receives an income as members must pay yearly dues, to develop and support its work. As such the documents developed by such groups belong to a different class of "standards", since they are not a standard according to the international definition of such documents.

Most of the work going on the Design Automation Standard Committee (DASC) which is the arm of the IEEE that addresses EDA issues, deal with either mixed-signal design, verification, and system level design. The work in Accellera targets both mixed-signal and verification. OSCI major work at the present is the development of the TLM 2.0 document, an important contributor to solving system level design issues. Only Si2, which has a greater number of members from the semiconductor industry than the other three organizations, continues to focus on fabrication issues dealing with support and use of the most advanced fabrication node available.

System level design is a market sector that has yet to be clearly defined by EDA vendors. At the moment none of the traditional EDA companies can claim to fully understand or support system level design, although CoWare has consistently claimed to know, and both Springsoft and Mentor have shown that they have some understanding of the software/hardware co-design and co-development problem. Startups, like Carbon Design Systems for example, are making progress in this area and may find it quite rewarding in spite of some pundits observing that "there is no money in selling software tools". I guess Microsoft or Wind River, for example, did not get their memos.

Having had the luxury of dealing with reality using the digital approximation for many years, system houses are now being forced to use analog design in order to realistically duplicate natural phenomena. Mixed-signal design is becoming a requirement for competitive products that serve the most promising sector, end-user products, like games, phones, and personal electronic appliances. Automotive and medical applications, two other sectors that are expanding significantly, also require analog and mixed-signal design.

As long as design verification continues to be a post-facto approach, it will remain expensive, and in fact, true to its history, the cost of verification will increase with the complexity of design. In spite of various efforts, we still have not found a way to develop a method to produce "correct by construction" designs. We have tried, with both languages and tools, but failed for different reasons. VHDL, for example, is a much more rigorous language than Verilog, and many design errors can be avoided simply by its use, but designers found the language to be too difficult and verbose, and opted to take their chances with Verilog instead. The Rosetta language, a very promising academic exercise, is languishing and the IEEE is now working on Estorel, a system level design language that has been used in Europe for a few years. Higher-level synthesis, like Catapult-C from Mentor or C-to-Silicon Compiler from Cadence are worthy efforts, but they have very limited capabilities to proclaim the original design bug free.

Conclusion
Obviously there are technological problems still to be solved. But the business plan must be different this time. The customers are not companies for which price is not an issue, capability is. The customers of the next few years are just as price sensitive as they are needy of new solutions. They have not grown stingy: they are addressing markets that offer far less profit margins, thus they must keep their own costs as low as possible. The most profitable EDA company in the next few years is not the one that can provide a solution to 22-nm design implementations at any cost, but the one that can offer the cheapest and most reliable set of tools to develop designs that use proven processes with demonstrated high yield capabilities.

See also:
Cadence reports poor results
Carbon Design Systems acquires SoC Designer from ARM