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Featured Design Center |
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Managing complex SoC verification using plan based verification techniques
Meeting the quality requirements of a complex SoC requires managing large verification projects. In this article, Freescale and STMicroelectronics recount a recent experience with a verification management solution (Incisive Enterprise Manager) from Cadence, for the verification of a 32-bit microcontroller project for the automotive industry.
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Analog/Mixed-Signal Design
PRODUCT HOW-TO: Efficient Fixed-Point Implementation of the Goertzel Algorithm on a Blackfin DSP
How to use the Goertzel algorithm flow and its fixed-point implementation on the Analog Devices Blackfin BF5xx processor its special arithmetic modes as well as how to efficiently implement 16.16 fixed-point multiplications.
JFET applications in today's analog world
Understand how this basic device fills a vital circuit function
A mixed signal approach to debugging DDR DRAM interfaces
This article highlights a few of the many challenges to using the new generation of DDR3 and LPDDR DRAMs in embedded systems and how intelligent use of a mixed-signal oscilloscope (MSO) can overcome them.
See all Analog/Mixed-Signal Design »
Board-Level Design
Easing the challenge of RF design (Part 2 of 2)
Designing in a wireless link need not be a nightmare--if you follow some simple guidelines
Understanding Factors Affecting Intel QuickPath Interconnect Signal Integrity (Part 2 of 2)
This article explores and explains key issues related to signal integrity in this interconnect scheme, as well as other parallel and serial differential bus designs
Reducing the Size, Cost and Complexity of RF Circuitry for the Next-Generation of Cellular Technology
Doing more of the same, but better, may not be the right tactic
See all Board-Level Design »
Electronic System Level (ESL) Design
Embedded system virtualization for executable specifications and use case modeling
To reduce the time-to-market of embedded system projects, virtual hardware platforms offer a method to develop hardware-dependent software and application software before production hardware is available. However, for true system-level specification and architecture optimization, full-system virtualization is required, including abstract models of HW, behavioral models of application SW and use cases.
Low power LDPC decoder created using high level synthesis
This article gives an example in which an HLS tool is used, together with architectural innovation, to create a low power LDPC decoder.
Book excerpt: 'Project management of complex and embedded systems'
The management of automotive design projects provides a window into how to handle other complex development and manufacturing efforts.
See all Electronic System Level (ESL) Design »
Digital IC Design
Reducing Costs, Risks, Time to Market with Virtualized Systems Development
To achieve developer efficiency and software quality with virtual system development tools, it is necessary to use a fully-featured simulation infrastructure with the ability to create custom models.
Time domain modeling and simulation of Intel QuickPath interconnect circuits (Part 1 of 3)
This article explores and explains key issues related to modeling and simulation in this interconnect scheme, but its lessons apply to other designs as well
Making packet processing more efficient with network-optimized multicore designs: Part 2
In terms of both power consumption, it is now feasible to build complete network packet processing designs using general purpose architecture processors, rather than dedicated ASIC and ASSP SoCs optimized for the application. Part 2: Minimizing/hiding latency.
See all Digital IC Design »
Verification
Managing Complex SoC verification using plan based verification techniques
Meeting the quality requirements of a complex SoC requires managing large verification projects. In this article, Freescale and STMicroelectronics recount a recent experience with a verification management solution (Incisive Enterprise Manager) from Cadence, for the verification of a 32-bit microcontroller project for the automotive industry.
Researchers propose commonsense plan to improve verification process
Researchers have proposed an integrated, all-encompassing plan for verification teams based on a commonsense approach and proper documentation of all aspects of the process
Layering it on--a new approach to automating system tests
Here's a layered approach to testing that uses pluggable software components to assure scalability and portability.
See all Verification »
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About the EDA DesignLine How-To Section
About the EDA SesignLine How-To Section
The EDA DesignLine How-To section delivers engineering articles focused on EDA tools; ESL design; verification; DFM; signal integrity; chip designs at 45, 65, and 90 nm, board layout, and system level design.
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