Analog/Mixed-Signal Design
Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs
The verification of analog/RF blocks presents challenges when using a digital fastSPICE simulator. The use of an analog fastSPICE simulator mitigates them.
Low Power Design For Analog/Mixed-Signal IP
Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase.
Analog and Mixed-Signal Design Tools Vendors Reference Chart
Reference chart of tools for Analog and/or Mixed-Signal design. Courtesy of Gary Smith EDA.
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Board-Level Design
Moving up to DDR2 at printed circuit board layout
Designing faster processors is the order of the day in the computing industry. However, processor speeds continue to exceed memory latency improvements.
PCB Tools Vendors Reference Chart
Reference chart for Printed Circuit Board (PCB) design tools. Courtesy of Gary Smith EDA.
Embedded developers should embrace FPGAs
The use of FPGA devices is a driving factor in the success of using software to reduce hardware complexity. The technique also provides an open-ended flexibility that comes from transferring the controlling elements of a design into programmable space.
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Electronic System Level (ESL) Design
Software-Defined Radio Platforms
A team at IMEC recently took the design complexity hurdle. They designed and demonstrated an SDR on MPSoCs, using advanced methods such as electronic system-level (ESL) design and co-emulation.
ESL Tools Vendors Reference Chart
Chart of ESL tools grouped by application areas courtesy of Gary Smith EDA.
Virtualization: Creating a new software development infrastructure
Software development is a fascinating industry that has changed over the years as developers have continually adopted newer programming languages, from Fortran to Pascal to C++ and beyond.
See all Electronic System Level (ESL) Design »
Digital IC Design
Serial ATA and the evolution in data storage technology
The SATA specification was developed with the fundamental goals of having a ten-year scalable performance roadmap.
What floorplan information is needed for synthesis
Creating custom wireloads based on a trial place-and-route is ineffective, because once synthesis begins structuring logic differently the logic structure - and therefore the placement and routing topology " will be different from the first model.
A Power Integrity Wall follows the Power Wall
Today, power consumption is the single dominant design constraint for integrated circuits, but less noticed, and even less respected is power integrity despite its undeniable role in determining power and energy consumption.
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Verification
Host Bus Adapter (HBA) Verification with Trek
A tool like Trek from Beker Verification Systems can speed Verification of a Host Bus Adapter.
Multi-language Functional Verification Coverage for Multi-site Projects
The second installment takes a deeper look at how powerful verification solutions can be constructed, and what other issues you may encounter while designing such a solution.
Verification IP Reuse For Complex Networking Asics
The use of a mixed language environment with SystemC and SystemVerilog for ASIC verification.
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About the EDA DesignLine How-To Section
About the EDA SesignLine How-To Section
The EDA DesignLine How-To section delivers engineering articles focused on EDA tools; ESL design; verification; DFM; signal integrity; chip designs at 45, 65, and 90 nm, board layout, and system level design.
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