Using fill synthesis for enhanced planarization (part 2)

Electrically Aware Approaches

1. Timing-Driven Fill
   Tools that use a purely geometric approach have no notion of timing or power. They blindly add fill shapes to sparse areas of the chip and, in doing so, may create timing violations by adding extra metal too close to timing-critical nets. It is possible to tell the fill tool to avoid adding fill shapes in specific areas. However, this is a very tedious and time-consuming process, unless there is an automated way to identify critical nets and prevent fill shapes from being placed too close to wires of those nets.
   

   Timing-driven fill solutions read timing constraints and/or standard timing reports, identify critical nets, and automatically avoid changing the parasitic characteristics of timing-critical wires. More complete solutions may prohibit fill shapes from being placed near wires of critical nets on adjacent layers as well. Figure 7 shows the blue areas where fill should not be inserted within a Metal-4 layout, due to timing criticality of net segments on Metal-4 as well as on adjacent Metal-3 and Metal-5 layers. The yellow "track fill" shapes (see the discussion of lithography-enhancing fill, below) avoid the blue areas.
   

   
   
   7. Left) In Timing"Aware Fill Metal-4 fill avoids close proximity to wires of timing-critical nets on Metal-4 and adjacent layers.
   

   Timing-driven fill is especially needed when using a timing-driven place-and-route tool. The timing-driven router will often use greater than minimum spacing rules for wires of critical nets, so as to reduce coupling capacitance. However, this exposes those wires to additional, unforeseen capacitance that is introduced when empty space is occupied by fill shapes. A timing-driven fill tool will recognize the wires as belonging to critical nets and avoid placing fill shapes too close to them.
   

   Some approaches advocate having the detailed router insert fill shapes since it has full knowledge of design rules and timing, and can add fill in compliance with such constraints. However, there are several drawbacks to this approach. First, routers often use abstracts in place of full layouts of hierarchical modules (cells and blocks). Without detailed knowledge of the internal contents of each cell and block, the router is not able to accurately measure density. Second, a detailed router has a very limited view of the chip because its shape synthesis only works on a small piece of the design at any given moment. Thus, it is difficult for the router to holistically manage density over the entire die area (and the entire layer stack) of the chip. Finally, with the myriad rules and objectives that a detailed router must deal with, its job is difficult enough without having to worry about fill. A separate fill synthesis tool is much better suited to performing the task after detailed routing has been completed.



2. Power-Driven Fill
   The same proximity avoidance technique used for timing-critical nets can also be applied for highly active nets " nets with high levels of switching activity " to control dynamic power dissipation. An intelligent fill solution reads power requirements and switching activity information from toggle-count or switch-factor design files, then avoids putting fill shapes on relevant layers near wires of those nets.


3. Symmetry
   Analog circuitry may impose special requirements and restrictions on metal fill. For example, symmetry may be critical to the proper operation of the analog circuit (i.e., with respect to differential or matched structures). In such contexts, the fill shapes must respect axes of symmetry in the relevant areas of the analog layout. Figure 8 shows the outline of an analog cell, the axis of symmetry, and the fill shapes that have been placed in a symmetric pattern about that axis.

Advanced Requirements

1. Multi-Layer Constraints
   Simple fill tools only consider one layer at a time. However, fill shapes placed on a lower layer can affect the surface contours of layers above. Post-CMP deposition of oxide in the BEOL is conformal; therefore, the topography variation of one layer is almost directly transferred to the layer above. Further, the topography variation of the upper layer can be additive with respect to the variation transferred from the previous layer. Even when the density variation of one layer is small, it is possible to have large enough variations for the entire back-end stack to cause yield loss or exceed the depth of focus limits of lithography. Intelligent fill synthesis simultaneously minimizes density variations of multiple layers as well as variations within each layer. Conventional fill synthesis cannot perform such a task.
   For example, fill shapes on one layer can affect the timing and power characteristics of wires on adjacent layers, both below and above. It is therefore important that the fill solution, in addition to optimizing for surface smoothness, not adversely impact the timing and power attributes of wires on all other layers. Figure 7 above showed that intelligent fill synthesis will refrain from placing same-layer, as well as adjacent-layer, fill shapes near wires of critical nets. Multi-layer interdependencies are also induced by new inter-layer density rules. For example, design rule manuals at 65nm and below will commonly prohibit three consecutive layers from all having maximum density within a given window.


2. Advanced Timing-Driven Fill
   An advanced timing-driven fill technique involves configuring the fill shapes around critical nets so as to reduce coupling capacitance, in contrast to regular pattern techniques that may not be able to distinguish critical wires from non-critical ones. Figure 9 illustrates how timing-driven "track fill" shapes preferentially avoid a timing-critical net segment. Track fill has the added advantage of enhancing the fidelity of the wire edges (more about this in the Lithography section below).
   
   
   
   9. Timing-driven "track fill" shapes preferentially avoid a timing-critical net segment.
   

   Figure 10 shows how clusters of fill shapes can be intelligently placed so as to minimize the amount of additional coupling capacitance that results due to fill.





10. The placing of fill shapes can minimize coupling capacitance.

3. Lithography-Enhancing Fill
   The use of "track" fill shapes instead of squares, as illustrated in Figure 9 above, will enhance the shape fidelity of surrounding wires. This technique is also important for non-metal critical layers.
   

   Historically, fill was first used only on metal layers. However, fill shapes are now routinely added to poly layer as well. At 65nm and below, adding fill shapes on poly layer not only reduces variations in ILD thickness, but also has the added benefit of enhancing line edge fidelity. Figure 11(a) illustrates a traditional fill synthesis where the distance from functional poly lines to dummy poly may be of forbidden pitch. Figure 11(b) on the other hand shows a more intelligent fill pattern where dummy poly lines are added to protect functional poly lines with legal pitches at all places.





11. (a) Traditional poly fill synthesis may violate poly forbidden pitch rules, (b) intelligent poly fill will not.

4. Shadow Fill
   "Shadow fill" controls metal density when using hard intellectual property (IP) blocks. The use of IP can cause problems because the density of the block is fixed; this forces the metal density of the area around the block to be adjusted to accommodate the block. If the block is very dense, then many fill shapes must be added, which could lead to power and/or timing violations as shown in Figure 12.
   
   
   12. Fill shapes required to balance density with hard IP block may impact timing or power of neighboring nets.
   

   Shadow fill shapes are added to the IP block during the development and hardening of the block. These shapes are configurable in the sense that they may or may not be used when the block is instantiated in the chip. Figure 13 shows, within the IP block, the wires that existed prior to fill, the "locked" fill shapes, and the "shadow" fill shapes. When the block is included in the final chip-level assembly, the locked fill shapes will always be present. However, the shadow fill shapes are configurable, and may or may not be present depending on the metal density of the surrounding area.
   

   If the IP block is being placed into an area where metal density is very high, then all shadow fill shapes will be used, as shown in Figure 13(a). In an area of medium density, only some of the shadow fill shapes will be used, as shown in Figure 13(b). Finally, in an area of low density, few or none of the shadow fill shapes will be used, as shown in Figure 13(c).

Page 2: Application to IC Products
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