Introduction
As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, which threatens to negate many of the benefits that smaller process geometries offer. Static timing analysis (STA) cannot properly account for the variability inherent in semiconductor processes, making exaggerated pessimism a necessary evil. Process variation " which at 90nm and above had a manageable impact on delay " has a much more dramatic effect as process geometries shrink. The reason this occurs is that process control becomes more difficult at smaller process nodes. Even if the amount of variation remained the same as in previous generations, it will account for a greater percentage of process geometries as they get smaller.
For instance, a 0.01μm variation at the 1um process node is only 1% of the nominal. However, the same 0.01μm variation at the 65nm process node is greater than 15% of the nominal. In traditional STA, this variability is accounted for by introducing more aggressive gross guard-band and new analysis corners to model different process and environmental variation combinations over multiple analysis runs. As the number of scenarios increases, the number of possible corners can increase greatly, making design convergence exceedingly difficult while straining resources, increasing costs, and negatively impacting schedule.
Statistics is emerging as the most likely vehicle to carry the industry forward into the future of timing analysis. Using a statistical approach it will be possible to break beyond the barriers of case analysis and begin to holistically model the factors affecting process variation in a single analysis run. This will not only obviate the need for corners but remove much of their inherent pessimism. The results will be in the form of a probability density function (PDF) " for instance a normal Gaussian distribution " which will indicate the probability of failure for a given timing slack, rather than the traditional slack number. This enables designers and management to evaluate parametric yield for a desired performance target " a key facet of Statistical Static Timing Analysis (SSTA).
Types of Variation: Die to Die and Within the Die
In SSTA as well as traditional corner-based STA, it is necessary to model the effects of variation across the wafer (Die 2 Die) and across the die (WithIn the Die, or WID). With SSTA, it is possible to take this a step further by more accurately modeling how variation affects timing " parameter by parameter, instance by instance, and wire by wire " rather than just applying a gross case analysis to the entire design. SSTA allows the designer to choose an acceptable probability of timing failure as a target for analysis. This timing yield represents the worst scenario for a given slack PDF curve for die to die (D2D) analysis. For instance, if the target sigma multiplier for setup time was +3 the target timing yield would be 99.9%. This differs from worst-case analysis in that the worst possible scenario is not chosen since it only has an exceptionally small probability of occurring (see Figure 1).
1. The probability of worst-case occurrence is low.
At 90nm and larger technologies, WID variation is minimal but at 65nm and below, the effect of process variation is large enough that when a simple guard-band technique is used the overall performance of the design is significantly reduced, virtually negating the advantages gained by moving to a smaller process node. Allowing timing analysis to understand how variation affects different areas of the design and paths with varying device proximities can reduce pessimism. With SSTA, instead of applying a gross margin to the entire design to account for local variation for all paths, the differences in variation due to location and relative position on the die can be modeled for each device and interconnect along a given path. Modeling the variation within the die is imperative for pessimism reduction on a path-by-path basis at smaller process geometries.
Modeling WID variation for interconnect parameters must include systematic process variation such as Chemical Mechanical Processing (CPM), Lithography as well as thermal variation. For devices, uniform process variation of device transistors (a.k.a. inter-gate variation) depends on proximity and inter-gate temperature and voltage variation depend on design characteristics and locale. Devices also experience random or intra-gate variations, which are related to device mismatch (non-uniform variation of transistors within same gates/cells) and are accounted for by the Pelgrom effect.
Spatial or mesh-based techniques can be used to model the amount of variation for interconnect and device parameters for different areas of the die. A spatial technique would involve defining how a particular parameter varies as a function of distance. You can employ a mesh-based technique by breaking the die up into a mesh and deriving a variation distribution for each parameter in each section of the mesh.
Sources of Variation and Statistical Modeling
Most SSTA solutions use a sensitivity-based approach to model the effect of variation on timing. This involves establishing how change in a particular device or interconnect parameter, such as oxide or wire thickness, affects a desired property, such as slew or capacitance. This "sensitivity" to the parameter in conjunction with its probability distribution (mean and standard deviation) provides a statistical model describing the probability that a parameter will have a certain effect on a device or interconnect property.
Foundries that support SSTA will need to break down and model the variation of device parameters and interconnect parameters in real silicon. This information will be used for statistical library characterization as well as statistical extraction. Device parameters could include oxide thickness, gate length and width, voltage threshold and interconnect parameters could include metal width, thickness, spacing and dielectric properties. A small subset of these parameters should be selected which have a significant impact on timing and used for characterization. Careful selection of parameters is important in order to keep the runtime for SSTA manageable while maintaining accuracy.
It is possible to then use this parameter variation information for timing analysis by generating models which define sensitivities to these parameters. For a device, these sensitivities represent how the change in a particular parameter affects delay, slew, setup, hold, etc., and are generated during library characterization. For interconnect, these sensitivities represent how a change in each parameter affects resistance, capacitance, and inductance, and are generated during extraction.
These sensitivities can then be used in conjunction with a probability density function (PDF) to provide the full distribution for each parameter. The parameter distributions could be either Gaussian or non-Gaussian distributions since the sensitivity is delay per parameter change and is not dependant on the probability function. The sensitivities can be either linear or nonlinear depending on the device parameter.
For instance, suppose that the nominal value for a particular device parameter P is 50nm varies by 䔮nm (taken at 3 standard deviations from the nominal) or from 40nm to 60nm and that the change in delay over this interval is 1000ps. The linear delay sensitivity (S) for a parameter (P) then becomes:
S = ΔP/ΔDelay = 20nm/1000ps = 0.02 nm/ps
Environmental variation such as instance voltage and temperature can also be modeled and accounted for with sensitivity-based techniques. Characterization for voltage, for example would require varying the voltage over a specified operating range an establishing a non-linear sensitivity to a change in voltage for slew, setup, etc. This would allow environmental effects to be included in the analysis of a path in conjunction with process effects and eliminate the need for inaccurate linear voltage derating techniques or multiple voltage libraries. Random variation must be accounted for separately for each device timing property. Random variation can be modeled by simply adding another sensitivity value and its distribution into the mix.
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