New EDA Tools Improve Low Power Design

Power-Sensitive Design Today: Difficulties and Shortcomings
Calculation of power is based on activity of the circuit, the capacitance, and the voltage, using the formula P = CV²f. This means that to reduce power, you have several variables to manipulate.
There are four main techniques used throughout the design flow. First, lower the voltage at the expense of performance, by providing lower-voltage power supplies to parts of the design; this introduces voltage domains in the design. Second, completely shutting off power to parts of the design will reduce power consumption; this isolates a power domain in the design. Third, reducing toggle activity of logic whose computational results are not being "listened to" will reduce power; this technique introduces clock gating into the design. Lastly, performing selective tradeoff of power versus performance, using only high threshold voltage cells where circuit timing is critical, will reduce power; this technique introduces multi-voltage threshold (multi V_t) cell substitution.
Figure 1 illustrates a typical power-sensitive design flow where these techniques are applied, though design teams may have variations on this flow depending on their design methodology and EDA tools.

1. During the architectural stage, the design team makes decisions about where voltage and power domains are needed. Creating such domains involves significant trade-offs between power savings, design complexity and performance. Each additional domain introduces complexity, with a worse-than-linear dependence. Assessing these trade-offs is essential to defining the optimal number of domains, a decision that in turn drives implementation later in the design cycle. Yet today, there is no good way to accurately gauge these trade-offs. Typically, designers resort to best-guess scenarios and back-of-the-envelope calculations. These decisions need to be made at the architecture level to effectively drive design implementation later in the design cycle.
2. After the architecture is defined and RTL development starts, designers plan for block-level clock gating. By this stage, voltage and power domains are frozen, and clock gating represents the next-biggest potential source of power savings. But in deciding where to insert the clock gate enables, designers have been hampered by the lack of tools for measuring the impact of such choices on power consumption — i.e., tools for accurately estimating power consumption at the early RTL level. Again, designers have had to resort to back-of-the-envelope calculations, and as a result clock gating has been error prone and inexact. Typically, this leads to time-consuming late-stage iterations to adjust clock gating during physical implementation (step 5, below).
3. Once the RTL has reached the point where the design can be simulated, some design teams perform their first power estimates. If the estimates show that power budgets will not be met, then further analysis and design modifications are required. Power estimation may be done using a simple spreadsheet, or commercial or home-grown tools. Power estimation tools typically allow evaluation of what-if scenarios, which can help guide designers with power tradeoffs. Examples of what-if questions include:
   • If we add pipeline stages to this datapath to reduce activity, does the clock power increase outweigh the savings?
   • If implementation is able to use 70% high-Vt cells in this block, how much static power will be saved?
   • If this block is turned off with a power domain instead of via global clock gating, how much static and dynamic power will be saved?

   The problem here is that the accuracy of RTL power estimation has traditionally been low, limiting the effectiveness of design modifications at this stage. Other design teams wait until after gate level implementation (step 5) before performing power estimation, but by then, RTL is frozen, which is months too late to make a significant RTL change.

4. As the RTL design progresses, a number of power-related verification tasks are required. For example, some teams insert level shifters (to shift voltage levels between voltage domains) and isolation logic (placed between power domains to maintain a known logic value for signals exiting a powered-off domain) at this stage. These changes must be verified against the design intent. For designs with multiple power domains, formal verification techniques could be used to ensure the proper sequencing of power-up and power-down for the domains. Some design teams use power-aware simulation to make sure that the X values introduced when a block powers down do not result in incorrect functional behavior.
   Difficulties arise at this stage because commonly used methods of inserting level shifters and isolation logic (i.e., manually or using scripts) tend to be error prone, complicating the verification task.
5. The implementation team generates a gate-level design representation and creates a physical design which captures the design intent. In previous chip geometries (130nm and above), power distribution via a single chip-wide network was usually sufficient. In today's designs, upwards of twenty different power networks may be needed, with appropriate level shifters and isolation logic between the domains.
   The challenge at this stage is that synthesis, place and route tools have not matured sufficiently in their comprehension of complex power management schemes and can't be relied upon to automatically specify the best physical implementation. For example, physical design tools attempt to automate the implementation of clock gating. But such tools only operate on explicit enables--ones which the designer has already specified. But many explicit enables in the design may achieve only a small power savings. In some cases, depending on the activity statistics, adding a clock gate may even increase the power. Implementation tools often "swamp" clock tree synthesis (CTS) with a large number of ineffective enables. Typically, significant manual intervention by physical designers is therefore required to save significant power with clock gating schemes; most run an automatic gating mechanism blindly and accept whatever results it generates.
   Some power management techniques can only be applied at the gate level and during the implementation phase. Most technology libraries include two or more Vt levels, to allow trading off performance vs leakage power. This swapping is typically done late in the implementation process. The technique can be generalized to allow any gate resizing; this includes aggressive resizing for power recovery. Advanced implementation techniques like MTCMOS (Multi-threshold CMOS) and SRPG (State Retention Power Gating) are also emerging for designs where standby power is a key concern.
6. Once implementation is complete, final verification of power management and distribution can be done at this level. Power verification includes not only level shifter and isolation logic, but also ensuring that all design instances are connected to the correct supply. Similar verification can be performed for MTCMOS and SRPG implementation. It is critical to compare against the original design intent captured during the architecture and design stages. Yet automated tools typically have no way to deduce the intent. Some may attempt to "reverse engineer" the intent by looking only at the implementation, but this will only validate consistency, not correctness toward original intent. As a result, successful verification requires significant manual effort. And the stakes are high: any design flaws missed at this stage (just prior to tape-out) can be exceedingly expensive.

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