Introduction
Design power closure and circuit power integrity in large and complex digital integrated circuit designs have become one of the main drains on engineering resources, thereby impacting the device's total time-to-market.
Increasing usage of battery-powered portable (often wireless) electronic systems is driving the demand for chips that consume the smallest possible amounts of power. At the same time as these products are becoming physically smaller, consumers have grown to expect increased functionality and to demand longer battery life. A modern cell phone, for example, may include features such as the ability to act as a personal organizer, play games, take and transmit pictures, connect to the internet, and so on. In spite of this increased functionality, however, a typical cell phone weighs less than 4 ounces, and customers expect the battery to last at least three hours when in use and five or more days while in standby mode.
At the other end of the spectrum, the sheer amount of power consumed by some devices can cause significant design problems. Consider, for example, a recently announced CPU that consumes 100 amps at 1.3 volts, which equates to 130 Watts! This class of devices requires expensive packaging and heat sinks. The heat gradient across the chip can cause mechanical stress leading to early breakdown, and physically delivering all of this power into the chip is non-trivial. Thus, even in the case of devices intended for use in non-portable equipment where ample power is readily available, power-aware designs can offer competitive advantages with respect to the size and cost of the power supply and cooling systems.
Whenever the industry moves from one technology node to another, existing power constraints are tightened and new constraints emerge. Power-related constraints are now being imposed throughout the entire design flow in order to maximize the performance and reliability of devices. In the case of today's extremely large and complex designs, implementing a reliable power network and minimizing power dissipation have become major challenges for design teams.
Creating optimal low-power designs involves making tradeoffs such as timing-versus-power and area-versus-power at different stages of the design flow. Successful power-sensitive designs require engineers to have the ability to accurately and efficiently perform these tradeoffs. In order to achieve this, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with – and applied throughout – the entire RTL-to-GDSII flow.
Furthermore, in order to handle the complex interrelationships between diverse effects, it is necessary to use an integrated design environment in which all of the power tools are fully integrated with each other, and also with other analysis and implementation engines in the flow. For example, varying cell sizes affects their associated currents (and power consumption), and this in turn affects the voltage drops associated with these cells. In order to fully account for the impact of voltage drop effects, it is important to derate for timing, on a cell-by-cell basis, based on actual voltage drops. The timing analysis engine should then make use of this derated timing data to identify potential changes to the critical paths. In turn, the optimization engine should make appropriate cell sizing changes to address potential setup or hold problems that appear as a result of the timing changes. Once again, this will affect the currents, which will affect the voltage drops, and so on. If any of these interrelationships are not addressed due to the lack of an integrated design environment, your competitors will beat you to the market with lower-power designs.
This paper first describes the most significant power dissipation and distribution considerations. It then introduces the capabilities required of a true low-power design environment that addresses these power considerations throughout the entire RTL-to-GDSII design flow.
Dynamic Power Dissipation
These discussions deals with circuits fabricated with complementary metal oxide semiconductor (CMOS) devices, because this is currently the most prevalent digital IC implementation technology. Dynamic power dissipation occurs in logic gates that are in the process of switching from one state to another. During the act of switching, any internal capacitance associated with the gate's transistors has to be charged, thereby consuming power. Of more significance, the gate also has to charge any external (load) capacitances, which are comprised of parasitic wire capacitances and the input capacitances associated with any downstream logic gates.
Consider a simple inverter gate, in which only one of transistors T1 and T2 is usually on at any particular time (Figure 1). When the gate is in the process of switching from one state to another, however, both transistors will actually be on simultaneously for a fraction of a second. This causes a momentary short circuit between the VDD (logic 1, power) and VSS (logic 0, ground) rails, and the ensuing crowbar current results in a transitory power surge.
Click here for Fig. 1
1. While the gate is switching, both transistors may be active simultaneously.
The amount of time the two transistors are simultaneously active is a function of their input switching thresholds and the slew (slope) of the input signal driving the gate.
One of the factors controlling the slew of the signal being presented to the inverter's input is the size of the transistors forming the logic gate driving this signal. These need to be sufficiently large such that the signal transitions fast enough to keep the amount of time the inverter's transistors are both active to a reasonable level (Trace b in Figure 1).
Now consider what happens if the driving gate's transistors are too large and the driving gate is overpowered. In this case, the power savings achieved by minimizing the time where the inverter's transistors are both on (trace a in Figure 1) will be negated by the driving gate having to charge the increased capacitance associated with its over-sized transistors, thereby consuming excessive amounts of power. Furthermore, the extreme speed of the signal's transitions will also cause signal integrity problems in the form of noise, overshoot, undershoot, and crosstalk.
By comparison, if the driving gate's transistors are too small and the driving gate is underpowered, the inverter's transistors will both be on for a significant amount of time (Trace c Figure 1), thereby causing the inverter to consume unwarranted amounts of power (the under-driven input signal will also be susceptible to noise and crosstalk coupling effects from other signals).
Addressing Dynamic Power Dissipation
For the purposes of this introductory paper, the amount of dynamic power dissipation may be represented using the following equation:
Dynamic Power ≈ αf x C x V2
Where:
αf = Amount of activity as a function of the clock frequency (f)
C = Amount of capacitance being driven/switched
V2 = The square of the supply voltage
This equation shows that minimizing the circuit activity and/or reducing the capacitance being driven and/or reducing the supply voltage may reduce the dynamic power dissipation.
One way to reduce the amount of switching activity is to reduce the frequency of the system clock. However, this will have a corresponding impact on the performance of the device. Another technique is to employ clock gating, which restricts the distribution of the clock to only those portions of the device that are actually performing useful tasks at that time. It is also possible to minimize local data activity (glitches and hazards) by applying appropriate delay balancing.
There are a number of ways in which the amount of capacitance may be reduced. One approach is to downsize the gates driving over-driven wires, thereby lowering the capacitances associated with these gates. Another technique is to use a power-aware placement algorithm to minimize the length of critical wires, which therefore reduces the size of their associated parasitic capacitances. This power-aware placement should ideally be based on (or weighted by) the amount of switching activity associated with each wire. Yet another alternative is to exploit technology options such as using low-k dielectric (insulating) materials and low resistance/capacitance copper (Cu) tracks.
Lowering the supply voltage dramatically reduces a logic gate's power consumption, but this also significantly reduces the switching speed of the gate. One solution is to use multiple voltage domains, which means having different areas of the chip running at different voltages. In this case, any performance-critical functions would be located in a higher voltage domain, while non-critical functions would be allocated to a lower voltage domain.
There are also interesting trade-offs that can be made between functional parallelism and frequency and/or voltage during the algorithmic and architectural stages of the design flow. For example, replacing one block of logic running at frequency 'f' and voltage 'V' with two copies of that block, each of which performs half of the task, and each of which is running at a lower frequency and/or a lower voltage. In this case, the total power consumption of this function may be reduced while maintaining performance at the expense of using more silicon real estate.
Static Power Dissipation
Static power dissipation is associated with logic gates when they are inactive (static); that is, not currently switching from one state to another. In this case, these gates should theoretically not be consuming any power at all. In reality, however, there is always some amount of leakage current passing through the transistors, which means they do consume a certain amount of power.
Even though the static power consumption associated with an individual logic gate is extremely small, the total effect becomes significant when we consider today's ICs, which can contain tens of millions of gates. Furthermore, as transistors shrink in size when the industry moves from one technology node to another, the level of doping has to be increased, thereby causing leakage currents to become relatively larger. The end result is that, even if a large portion of the device is totally inactive, it may still be consuming a significant amount of power. In fact, static power dissipation is expected to exceed dynamic power dissipation for many devices in the near future.
Addressing Static Power Dissipation
There are two key equations that need to be considered when it comes to addressing static power dissipation. The first describes the leakage associated with the transistors:
Leakage ≈ exp ( -qVt / kT )
One important point about this equation is that it shows that static power dissipation has an exponential dependence on temperature (T). This means that as the chip heats up, its static power dissipation increases exponentially.
Another important point is that static power dissipation has an exponential dependence on the switching threshold of the transistors (Vt). In order to address low-power designs, IC foundries offer Multi-Vt technologies that enable multiple Vt libraries. This means that each type of logic gate is available in two (or more) forms: with low-threshold transistors that switch quickly but have higher leakage and consume more power, or with high-threshold transistors that have lower leakage and consume less power but switch more slowly.
The second equation describes how the delay (switching time) associated with a transistor is affected by the switching threshold of that transistor (Vt) and the supply voltage to that transistor (VDD):
Delay ≈ VDD x (VDD " Vt)-α
This means that engineers have to perform a complicated balancing act, because lowering the supply voltage reduces the amount of heat being generated, which in turn lowers the static power dissipation. However, lowering the supply voltage also increases gate delays. By comparison, lowering the transistors' switching thresholds speeds them up, but this exponentially increases their leakage and therefore their static power dissipation.
One solution is to use multiple voltage domains as was introduced in the discussions on dynamic power dissipation above. Another option is to use low Vt transistors only on timing-critical paths, and to use high Vt transistors on non-critical paths. These two solutions may of course be used in conjunction.
Yet another technique is to selectively power-down leaking blocks using non-leaking transistors (MTCMOS switches) whenever those portions of the device are not required; for example, when those portions are placed in a "stand-by" mode. However, switching entire blocks on and off can cause dramatic current surges, which may require the use of additional circuitry to provide a "soft" (staged) power on/off for these blocks.
Click here for Fig. 2
2. Power distribution considerations include total power consumption, voltage drop, and electromigration effects.
|
