Introduction
The electronic design industry continues to push the limits of Moore's Law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures.
Physical and electrical effects at this node challenge both design closure and time to market, and the requirements for design signoff are changing in order to address the inherent manufacturing and process variability. Naturally, this situation can seriously undermine the manufacturability of the design. In fact, a paradigm shift is evident in the all-important signoff analysis step of the digital design cycle.
At issue are the levels of validity and confidence that can be reached with today's IC design closure and signoff methodologies. Designs that pass traditional sign-off standards might still fail in 45nm silicon. In contrast, using excessive guard-bands or over-conservative margins to satisfy traditional static timing analysis (STA) signoff regimes can negate the benefits that smaller process geometries offer.
This article looks at some of the electrical, physical, and manufacturing challenges to current signoff analysis methods, and shows new ways to improve predictability, productivity and performance at the 45nm process node. Using these new methodologies, designers can prevent silicon failures and better manage timing, leakage power, and signal integrity " both across a wafer and across the surface of a single chip.
Traditional signoff analysis - running out of steam
Figure 1 illustrates how predictability in design schedules has diminished as the previously small, variable segment of the schedule has grown to dominate the overall schedule on complex projects at smaller process geometries.
1. At the 45 nm process node we have a predictability crisis.
If design complexity is normalized to 1X at 180nm, then design complexity at 65nm has significantly increased to 30-40X. Typically, design schedule variability is fairly contained at 180nm and is close to 10% over the planned design schedule. However, at 65nm the variable portion can be larger than the planned portion. And at 45nm, due to the advanced variation challenges, the schedule can potentially go completely out-of-control leading to major crisis situations.
One strong reason for this lack of predictability and also a cause of diminishing productivity is the current disconnect between the analysis performed during implementation and the signoff verification required by the foundry. In addition to being utilized by completely different groups, the implementation and signoff tools employ different engines, which means the signoff analysis may detect problems that were not apparent during the implementation process. Fixing these problems can cause a ripple-on effect and generate new problems, which makes the process of achieving design closure extremely time consuming. Even worse is the fact that majority of today's implementation flows employ different engines for each of the tools in the flow. For example, the clock tree tool may use a different timing engine than the placement tool; in turn, the placement tool may use a different engine than the routing tool, and so on.
Another critical challenge for existing signoff solutions is the performance bottleneck brought on by the need to analyze an increasing number of electrical integrity and variability effects at 45nm. For example, the number of wires has increased significantly and so has the number of interactions between these wires. This leads to explosion in the number of signal integrity issues. Advanced techniques are needed to efficiently separate the handful of real problems from the plethora of false positives.
Variability is the Achilles' heel
The process of manufacturing an integrated circuit is inherently imperfect. Slight variations in the duration, temperature, and chemical concentrations at each step result in variations from one wafer to another, between die on the same wafer (inter-die), and between cells and interconnect on the same die (intra-die). These manufacturing variations result in physical changes in devices and interconnect leading to deviations in their electrical behavior. At 45nm process control is difficult, and even if the absolute amount of process variation remains the same as in previous generations, it accounts for a greater percentage change in overall performance at the smaller node.
Traditional static timing analysis (STA) cannot properly model the variability inherent in semiconductor processes. It compensates for this variability by requiring aggressive guard bands and by using multiple corners or scenarios to reflect different manufacturing conditions. But as the number of scenarios increases, the number of analysis runs can increase greatly, making design convergence exceedingly difficult while straining resources, increasing costs, and negatively impacting schedule. At the very minimum, current STA solutions need to have distributed processing capabilities to handle concurrent multi-corner analysis and thereby mitigate the compute burden. Unfortunately, the corner-based approach is also overly pessimistic since it can report timing scenarios that have an extremely small likelihood of occurring. For this reason, statistical static timing analysis (SSTA) is emerging as the signoff vehicle to carry the industry into the future.
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