|
Phase lock loops (PLLs) play a key role in today's thriving RF industry. Commonly employed to address various timing requirements in ASIC designs, these basic building blocks allow designers to multiply clock frequencies, correct clock duty cycles, and cancel out clock distribution delays. Using inexpensive, low-frequency crystals as an off-chip clock source, designers can use PLLs to multiple the frequencies on-chip and produce various high frequency internal clock signals.
While they seem simple enough in structure and function, PLLs present some unique design challenges. Typically these functions include two widely-spaced time constants and a VCO that oscillates thousands of times faster than the reference frequency. In wireless systems, for example, the VCO often oscillates more than 5000 times faster than the reference frequency. But as IC manufacturers move to nanometer-scale process technologies, PLL performance faces increasingly stringent noise limitations. Such factors can introduce time-varying offsets in the phase of the output clock from its ideal value or jitter which can have disastrous effects on internal timing paths. These effects, in turn, can lead to setup time violations or impact off-chip interfaces by creating setup and hold time violations which lead to data transmission errors. Moreover, other issues including instability, inadequate frequency range, locking problems and static-phase offset can also impact PLL design. Ultimately, any failure to properly characterize PLL performance and detect these issues early in the design cycle can lead to major design issues later in the cycle.
Unfortunately, current simulation tools offer only limited help. Designers can use FastSPICE simulations to verify PLL performance at the transistor level. But the real challenge lies in optimizing those simulations. More often than not, the engineer doesn't know when to simulate at the behavioral level and when to simulate at the transistor level, and how each strategy will impact the design. Inevitably designers resort to a transistor-based simulation to ensure high levels of accuracy. But those simulations can take weeks to complete and the designer often ends up with unmanageable results.
New Strategy
Recently Cadence has proposed a new approach to meeting these design challenges. As part of the Cadence® RF Design Methodology Kit, Cadence engineers have developed a new strategy for characterizing PLLs using behavioral modeling to accelerate the design process. The new methodology is centered around a simulation guide. The purpose of the guide is to instruct the engineer step-by-step in how to model and characterize a PLL with transistor-level accuracy. The process starts with modeling of basic PLL building blocks and exploration of the many challenges that task presents. As part of this process, the guide offers insight into key design tradeoffs in loop Bw and lock time. Next, this new methodology steps the engineer through the key considerations in dimensioning and budgeting a PLL. Once that task is complete, the new methodology guides the engineer through a comprehensive simulation strategy at both the individual block and full PLL level.
From there, the engineer can step through test benches to perform core measurements and build a baseline for the design. With this foundation designers can explore the individual PLL blocks and characterize them to simulate a complete PLL. To maximize simulation accuracy, the methodology includes a new Perturbation Projection Vector (PPV) tool which automatically calibrates models of the various PLL building blocks to accelerate top-level simulation and verification including noise. Once the simulation is run, the designer can examine the results, apply advanced PLL jitter analysis, and validate the PLL at the transistor level.
Design Exploration
The key innovations in this new methodology begin at the design exploration stage of the development cycle. During the design exploration stage when engineers want to prototype their PLL and run "what-if" analyses, designers need a representation of the PLL that will allow them to run simulations quickly and efficiently. Short simulation runtimes allow the designer to quickly alter component values or the architecture of the low-pass filter (LPF) or drive current from the charge pump and look at the impact of these changes on overall closed-loop characteristics such as settling time, loop bandwidth or phase noise.
One way to accomplish this is to represent the PLL loop using linear phase domain modules built from standard components available from Cadence's analoglib library and run on the Cadence Virtuoso Spectre® Circuit Simulator. This technique allows designers to select a LPF transfer function, charge pump current and voltage controlled oscillator (VCO) gain and examine how much noise, including flicker noise, each block contributes to the design. This approach offers simulation run times as much as 250,000 times faster than transistor-level simulations and, thereby, allows the designer to modify parameters and rerun simulations to determine the best architectural solution. The one disadvantage to this approach is that it does not model non-linear behavior and, therefore, does not allow users to observe characteristics like cycle slipping or reference spurs. However, those non-linear behaviors are addressed later in the simulation process.
The schematic illustrated below (see Figure.1) offers an example of a testbench which can be used to model both flicker and white noise contributions. Reference input phase noise is estimated from commercial crystal oscillators. Phase-frequency detector (PFD) referred noise is curve-fit for transistor level noise simulation, assuming that the major contribution is from the resistor in the LPF. An artificial noise spike is added to define the reference spur location and demonstrate loop filter suppression effect.
1. PLL Linear Phase Domain Model for Loop Dynamics and Noise Contributions. This sample testbench models both flicker and white noise contributions.
Click here for a larger version
Using the Virtuoso Analog Design Environment (ADE) the user loads the simulation state and sets the limits for three different analyses (see Figure. 2). Next, in an ADE window, the user sets the plotting mode setting to append and selects Simulation -Netlist and Run to initiate the simulation.
2. Since the simulation runs so quickly, the limits for these three different analyses can be adjusted by the user as needed.
Click here for a larger version
To see noise contributions from individual noise sources, the user sets design variables to one at a time. Each variable controls the three sources of noise in the schematic and may be run simultaneously or individually. The images in Figure 3 illustrate how the designer can view the noise contributions from each source and overlay the noise plots or examine their performance impact as the charge pump current is altered.
3. The tool can be configured to show plots of noise contributions from individual noise sources.
Click here for a larger version
Identifying Charge Pump Non-idealities
While the short simulation runtimes in this first phase are advantageous for "what-if" analysis, PLL designers require more accurate predictions of circuit behavior to identify the effects of charge pump non-idealities in the PFD/CP, such as dead zone, current mismatch, offset current and jitter, to predict phase noise performance of the PLL. One way to achieve this goal is to use more detailed Verilog-A models of the blocks in the PLL. By examining noise performance, including flicker noise, in the non-linear loop, designers can refine the selection of system parameters and more accurately characterize the non-linear nature of the loop. The use of more detailed models increases simulation runtime. But by combining the divider block with the VCO, which removes the high frequency output of the oscillator from the simulation, simulation runtime is kept relatively short.
In the example below, designers used Verilog-A models with the Spectre Circuit Simulator to identify parameters such as settling time, loop bandwidth, phase noise and reference spurs. The plot in Figure 4, for example, illustrates a typical result for settling time characterization. The Min/Max range on the y-axis is adjusted to -100 to 100 and the Major/Minor subdivisions to 20 and 5.
4. Settling time characterization.
Click here for a larger version
One of the biggest challenges for any PLL designer lies in characterizing difficult to model non-linear effects such as injection pulling/locking or power supply noise rejection behavior. Typically this requires the accuracy associated with transistor-level models. But the simulation runtimes for those models can take weeks.
A new alternative approach uses Perturbation Projection Vector (PPV)-generated behavioral models to deliver transistor-level accuracy of the VCO in much shorter runtimes. This new methodology uses a SpectreRF simulation of the VCO circuit to create a table-based model that accurately represents the behavior anomalies of the transistor to mimic the closed-loop performance of the PLL. Yet simulation runtimes can run 500 to 10,000 times faster than comparable Spectre transistor-level simulations.
In the example below, the designer uses the SpectreRF Option of the Spectre Circuit Simulator to measure parameters such as settling time, injection pulling or locking threshold current, phase noise with injection pulling or locking and power supply noise sensitivity. The engineer begins with the design schematic and selects the VCO_PLL cell. The cell is converted to current source injecting into the VCO LC tank using the Virtuoso Schematic Editor. The vco_bench schematic remains unchanged and the PLL-VCO probe connections are modified to experiment with different perturbation nodes.
The designer then enables the SKI plug-in for the PLL macro model. The designer next reviews the analyses details and selects pss in the Analysis form. By selecting simulation>netlist and Run, the designer can generate the PPV model in as little as a few minutes. Using the Virtuoso Schematic Editor, the designer can load the simulation state and run the simulation using the new model. The graph below (see Figure 5) offers a sample plot of settling time characterization using the new PPV model.
5. PPV-generated models can be used to simulate non-linear behavior of the VCO and its impact on the PLL. The sample plot above depicts settling time characterization using a PPV model.
Click here for a larger version
Using Detailed Voltage Domain Models
Certain individual blocks within a design, such as dividers, may require more accurate simulation to debug and verify PLL functionality. In these cases the designer can use more detailed voltage domain block-level models to more closely represent the final architecture of the design. Typically, the designer can use tools such as the Virtuoso AMS Designer Simulator which supports the use of Verilog or VHDL, VerilogA codes, and schematics at the same time.
This strategy enables designers to confirm that digital and analog sections of the design are operating together without resorting to transistor-level simulations. It also allows designers to debug digital-only blocks which can be represented by actual RTL. However, this additional level of accuracy comes at the cost of longer simulation runtimes than when using other voltage domain models.
Finally, to acquire the most accurate predictions of circuit behavior, designers performs traditional "bottom-up" characterization of the design using transistor-level modeling. Here designers use tools such as the Virtuoso UltraSim Full-Chip Circuit Simulator to characterize the design. This approach requires relatively long simulation runtimes. Tools of this type typically offer a number of features to minimize simulation runtime without impacting accuracy, including circuit partitioning, the use of simplified model representations for less model-sensitive blocks, the use of more relaxed accuracy settings on slower speed digital circuits, and RC reduction techniques in lower speed digital circuits to reduce netlist size.
Conclusion
PLL design poses a key challenge in RF design. Escalating noise limitations and increasingly aggressive performance requirements demand simulation strategies that allow designers to characterize performance to high levels of accuracy quickly so they can identify any architectural issues early in the development cycle. By leveraging the latest advances in behavioral modeling and RF tool design, engineers can now take advantage of near-transistor-level accuracy without incurring the long simulation runtimes traditionally associated with that approach.
About the Author:
Bob Mullen is a Senior Member of the IEEE. He received his BS degree from San Jose State University, MSEE from Santa Clara University in 1985, and course work in Wireless
Communications from 1999-2001.
|
