Building better memory management for high performance wired/wireless networks: Part 2
The authors evaluate the performance of variable- versus fixed-size memory pools in tests implementing the two approaches for LTE and WiMAX protocol stacks
Building better memory management for high performance wired/wireless networks: Part 1
The authors describe a variable pool memory management scheme that has been implemented for LTE and WiMAX protocol stacks and has exhibited excellent performance, especially when compared to traditional fixed-pool implementations.
Ensuring the thermal integrity of your IC package/PC board design
Some basic tests will verify your PCB/IC thermal modeling and reality
A silicon-proven interoperable PDK
In 2009, TSMC announced the availability of the industry's first interoperable process design kit (iPDK). An iPDK benefits the entire TSMC design chain. TSMC customers will be able to use one unified iPDK to provide advanced functionality across multiple EDA vendor tools, improve design accuracy, shorten design cycle times, and promote design reuse.
FPGA design methods for fast turn around
Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
Functional programming paradigm and concurrency
This article introduces functional programming paradigm and shows how the industry is taking it forward to achieve more parallelism on concurrent systems.
How to inexpensively design an ASIC in 5 weeks
What many engineers may not know, hence a key motivator for this paper, is that a new generation of ASIC, (dubbed the NEW ASIC), is gaining momentum as an alternative to both standard cell ASIC and FPGA design.
Incorporating quality into reusable IP
How do you incorporate quality into reusable IP? This white paper is about how it is done at Arasan Chip Systems, Inc.
High-level synthesis, verification and language
The preferred high-level design methodology proceeds from high-level code to RTL code. Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.
Time Domain Modeling and Simulation of Intel QuickPath Interconnect Circuits (Part 3 of 3)
This article explores and explains key issues related to modeling and simulation in this interconnect scheme, but its lessons apply to other designs as well
Development of a Spice Op-Amp Macro-Model (Part 1 of 2)
Understand how a model is developed and validated
Tuning C/C++ compilers for optimal parallel performance in multicore apps: Part 2
Max Domeika, author of "Software development for embedded multicore systems," details C and C++ compiler scalar optimization and performance features that will allow you to take full advantage of parallelism via multithreading or partitioning. Part 2: The Compiler Optimization Process.
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