When combined with advances in FPGA technologies that ease complex interface design efforts, Chronology's TimingDesigner can simplify design issues and provide advanced accurate control of high-speed source-synchronous memory designs. This article explores a technique for determining necessary clock skew for balanced read data capture margins with DDR memory interface designs.
Designing FPGAs with the high-speed interface technologies available today helps you meet market demands, but it also presents some interesting design challenges. To ensure accurate data transfer for memory interfaces that operate at 200 MHz and beyond, timing analysis needs to play a more prominent role in the identification and resolution of system operation issues. At these frequencies, the margins for setup and hold times are tight, leaving minimal room to secure an accurate data capture and presentation window. Faster edge rates also magnify physical design effects, which cause signal integrity issues that require additional settling time, shrinking timing margins further.
FPGA devices now include advanced features that directly support Double Data Rate (DDR) interface technology within the I/O blocks, and on-board phase locked loop (PLL) networks for accurate clock control. These advances in FPGA technology help reduce the interface design effort by providing advanced building blocks.
When designing FPGAs with high-speed interfaces, detecting timing problems early in the design process not only saves time but also permits much easier implementation of design alternatives. TimingDesigner from Chronology allows you to create interactive timing diagrams for capturing interface specifications, analyze component interface timing characteristics, and communicate design requirements among project engineering teams (Fig 1). In addition, TimingDesigner contains features that allow exchange of critical timing data with FPGA tool sets throughout the design process. TimingDesigner can communicate place and route constraints that reference design specific timing measurements, and allows direct use of post place-and-route timing information to provide visual verification of the interface signal relationships required for desired FPGA interface operation.
1. TimingDesigner's GUI windows allow easy capture
of design interface characteristics.
(click this image to see a larger, more detailed version)
DDR/QDR memory interface design problem
DDR and/or Quad Data Rate (QDR) memory devices provide and accept source-synchronous data at twice the rate of the device's clock frequency. This means that data is transferred on the rising and falling edges of the capture clock. In addition, these devices require capture clock skew adjustments to ensure proper clock/data relationships. As noted earlier, several FPGA devices now include DDR interface technology support within I/O blocks and on-board PLL networks. In using these advanced building blocks, you need to conform to memory design requirements. This means that you have to have a way to manipulate the blocks accurately and reliably. To illustrate this point, let's take a look at a design requirement for a read operation with a QDR II SRAM source-synchronous interface.
In synchronous memory systems such as QDR SRAM, data is presented coincident with a provided clock, so clock derivatives must be created that are shifted by 90 degrees in order to safely latch memory data. This phase shifting is commonly referred to as center-alignment of the clock within the data valid window and is an important QDR design characteristic for accurate data capture (Fig 2). To shift the clock for a center-alignment, we can simply delay the clock signal by phase shifting using the PLL network on board the FPGA.
2. Illustration of center-aligned clock/data relationship.
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Capturing read data
Delaying the clock signal to achieve center-alignment ensures that various temperature changes and other similar effects the design may encounter won't cause an excessive amount of shift in clock/data position and therefore violate the setup or hold time requirements of the receiving register. In theory, a center-aligned clock edge will maximize the setup and hold times for most devices, allowing sufficient safety margins for drift. However, unless the setup requirement is equal to the hold requirement, center-alignment of the clock signal will provide more margin for one than the other.
The ideal solution is to provide a maximum safety margin for both setup and hold requirements of the device, which translates to balancing the margins, providing equal amounts of safety for both. To balance the margins, we determine the minimum data valid window for the receiving device, and center that window within the actual data valid window provided from the memory device given our design parameters.
Using the minimum setup and hold characteristics of our receiving device, we determine a minimum "safe" data valid window with the following formula:
Minimum Setup + Minimum Hold = Minimum Data Valid Window
The resulting data valid window is centered within the actual data valid window provided by the memory device, as shown in Fig 3. To ensure data capture, the data bus must transition within the indicated "safe" regions outside of the receiver's minimum data valid window. With this clock/data relationship, we ensure the maximum possible safety margin for read data capture when the design experiences signal drift in either direction.
3. Balancing the minimum Data Valid window within actual Data Valid window.
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Achieving proper clock skew
Skewing the source-synchronous clock will effectively shift the minimum data valid window of the receiving registers in the memory controller, and will therefore serve as the mechanism for balancing the data valid window. Clock skew adjustments are made with one of the PLL components inside the FPGA device. To determine the skew value, we must take into account routing delays and any external delay mechanisms that will affect the signal relationships.
We start by using TimingDesigner to create a diagram for the read operation of the QDR SRAM directly from the memory datasheet (Fig 4). We use this diagram to determine the clock and data signal timing relationships as they appear at the pins of the memory device as well as the data valid window characteristics of the design. The objective is to begin at a point where the signal relationship is well defined (the memory device), and propagate that relationship across the PCB to the FPGA where the unknowns begin to have an impact.
4. QDR Memory Read timing diagram for MT54W1MH18J.
(click this image to see a larger, more detailed version)
This figure shows how the PCB propagation delay is accounted for in the clock (CQ_FPGA) and the data (Q_FPGA) signals as they appear at the pins of the FPGA. Using separate variables in TimingDesigner's dynamically linked parameter spreadsheet allows easy variation of PCB delay values while showing the effect on the associated signals. We can now fit the design into the FPGA device to obtain the internal routing delays and determine the correct phase shift necessary for the capture clock.
