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This article is the second part of the two part article covering Topology Planning and Topology Routing. The first part covered a Design Engineer capturing Intellectual Property (IP) for a unique circuit and collaboration of this IP through the remaining design flow of a PCB. This second part focuses on the PCB designer collaboration of the IP and further employing Topology Planning and Topology Routing tools to support the IP and complete the PCB design.
Part one can be found at:Capturing and Sharing Intellectual Property in PCB Design
Topology Work Flow
In Figure 1, we see the role of the design engineer capturing IP by placing the few necessary components and planning critical interconnect flow between these components. Once captured this information is seamlessly provided to the PCB designer where they can complete the remaining design.
1. Flow of PCB design with design engineer capturing IP and seamless integration with PCB designer to finish design.
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Rather than going through the interactive and iterative process between engineer and designer to capture the correct intent, the design engineer has captured this information and done so accurately making it useful to the PCB designer.
For so many designs, the engineer and designer go through an interactive placement and routing, consuming both professional's valuable time. Historically, it is a necessary interaction, yet with time consuming inefficiencies. The original plan provided by the engineer may have been a hand sketch without appropriate scales of components, bus widths or pin outs.
As the designer engages with the design, placement of certain components and interconnect are captured by the engineer using topology planning techniques. Yet, the design is not complete with other components to place and probably other IO and bus structures to capture and all interconnects complete.
Like the design engineer, the PCB designer employs topology planning while interacting with both placed and unplaced components. Working this scenario produces the optimum placement and interconnect plan " providing density efficiencies.
As critical and dense areas are placed and topology plans captured, placement may be completed prior to the finished topology plan. Therefore, some topology paths may have to work with existing placement " they're a lower priority, yet still need to be connected.
Detailed Topology Planning
So a portion of planning occurs around placed components. Further, this level of planning may require greater detail to provide the necessary priority for other signals. The example shown in Figure 2 is of detailed planning after components are placed. There are seventeen bits to plan for this bus and they have a fairly organized flow.
2. These Bus' net lines are the outcome of higher priority topology planning and placement. So, a topology plan will be created to address this bus without manipulation of component placement.
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To plan this bus, the PCB designer considers the existing obstacle, layer rules and other important constraints. With these inputs they plan the following topology path for this path as shown in Figure 3.
3. The bus is now planned.
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In Figure 3, detail "1" has planned for the component pins on the top layer "red" to escape the component pins and join a topology path at detail "2". This is done with an unpacked area with only layer 1 identified as a routing option. This may seem obvious at this point of the design and the routing algorithm would use the top layer to connect to the red topology path. However, obstacles might provide other layer options to the algorithm before auto-routing this particular bus.
As the traces get organized into a packed path on layer 1, the designer then plans a transition at detail "3" to layer 3, to take the bus the distance throughout the PCB. Note, this topology path on layer 3 is wider then the top layer – the path is considering the additional space needs to accommodate impedance. Further, the design has also specified the exact location for layer transitions – or 17 vias.
As the topology path drops through mid right section of figure 3 at detail "4", many single bit T junctions are needed to escape from the topology path of connections to individual component pins. The designer's preference is to keep most of the connection flow on the layer 3 and breakout to other layers for connection to component pins. Therefore, they draw a topology area indicating connections from the main bundle to layer 4 (pink) to make these single bit T junctions to layer 2 and then use another via to connect to the device pins.
The topology path continues on layer 3 to detail "5" to connect to the active device. These connections then go from the active pins to pull-down resistors below the active device. The designer uses another topology area to specify connections from layer 3 to layer 1, where the component pins reside for both the active device and pulldown resistors.
This level of detailed planning only takes about 30 seconds to complete. Once this plan is captured, the designer may want to immediately route or create further topology planning and then auto-route all the topology plan. The auto-route results, following the plan takes less than ten seconds. Yet this speed doesn't matter and in fact is wasted time if the intent of the designer is ignored and auto-route quality is poor. The next figures show the auto-route results.
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