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Most Popular Articles |
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Author/Company |
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Date/Type |
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1
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Understanding Clock Domain Crossing Issues
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Saurabh Verma, Ashima S. Dabare, Atrenta
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Dec 24, 2007
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2
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FPGA design methods for fast turn around
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Angela Sutton
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Mar 04, 2010
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3
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The Different Types of UPS Systems
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American Power Conversion Corp.
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Oct 28, 2004
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4
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A silicon-proven interoperable PDK
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Rich Morse, SpringSoft, and Tom Quan, TSMC
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Mar 05, 2010
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5
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High-level synthesis, verification and language
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John Sanguinetti, CTO of Forte Design Systems Inc.
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Feb 22, 2010
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6
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Complex SoC Testing with a Core-Based DFT Strategy
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Sandeep Kaushik, Synopsys and Paul Policke, Qualcomm
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Feb 26, 2008
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7
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Utilizing Clock-Gating Efficiency to Reduce Power
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Mitch Dale, Calypto Design Systems
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Jan 15, 2008
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8
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Simplifying PLL Design
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Bob Mullen, Cadence Design Systems
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Feb 12, 2008
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9
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How to inexpensively design an ASIC in 5 weeks
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Narinder Lall
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Mar 02, 2010
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10
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Xilinx Virtex-6 FPGA User Guide Lite
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Peter Alfke, Xilinx Inc.
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Jul 22, 2009
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11
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Embedded system virtualization for executable specifications and use case modeling
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Vincent Perrier, CoFluent Design (Nantes, France)
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Jan 26, 2010
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12
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Applying Constrained-Random Verification to Microprocessors
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Jason C. Chen, Synopsys Inc.
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Dec 10, 2007
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13
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Using OVM to reuse vital verification knowledge
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Jana Richards, LSI Corp. and Dan Cohen, Mentor Graphics
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Jan 05, 2010
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14
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Preserving The Intent Of Timing Constraints
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Sridhar Gangadharan, Ramesh Dewangan, Atrenta Inc
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May 17, 2008
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15
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Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs
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Yiqun Lin, Silicon Laboratories
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May 13, 2008
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16
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Process Intelligent Modeling and Statistical STA improve DFM
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Prashant Maniar, Amit Majumdar, Hitendra Divecha, Stratosphere Solutions, Inc., Michael Jacobs, Rahul Deokar, Cadence Design Systems
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Sep 11, 2007
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17
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Functional programming paradigm and concurrency
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Aditi Athavale and PushpRaj Agrawal
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Mar 02, 2010
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18
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EDA 3.0: So you are an EDA startup?
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Tom Kozas and Michael Sanie
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Mar 17, 2009
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19
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Rigorous Automated Verification Yields High Quality Silicon
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Henry Angulo, Asad Khan and Scott Morrison, Texas Instruments Incorporated
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Apr 24, 2007
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20
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A Power Integrity Wall follows the Power Wall
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Raj Nair, Anasim Corp.
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Apr 08, 2008
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21
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Topology Planning and Routing
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Dean Wiltshire, Mentor Graphics Corporation
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Jul 30, 2007
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22
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Low Power Design For Analog/Mixed-Signal IP
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Navraj Nandra, Synopsys
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Mar 04, 2008
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23
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Hands-on: Get started in analog IC design and fab (Part 2 of 3)
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Stephen H. Lafferty
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Jun 11, 2009
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24
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Early verification cuts design time and cost in algorithm-intensive systems
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Ken Karnofsky, senior strategist for signal processing applications, The MathWorks
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Jan 22, 2010
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25
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Serial ATA and the evolution in data storage technology
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Mohamed A. Salem, Mentor Graphics Corp.
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Apr 28, 2008
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