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Most Popular Articles

 
  1   Understanding Clock Domain Crossing Issues   Saurabh Verma, Ashima S. Dabare, Atrenta
  Dec 24, 2007
  2   Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs   Yiqun Lin, Silicon Laboratories
  May 13, 2008
  3   Serial ATA and the evolution in data storage technology   Mohamed A. Salem, Mentor Graphics Corp.
  Apr 28, 2008
  4   The Different Types of UPS Systems   American Power Conversion Corp.
  Oct 28, 2004
  5   Simplifying PLL Design   Bob Mullen, Cadence Design Systems
  Feb 12, 2008
  6   Software-Defined Radio Platforms   Bart Van Poucke, Bruno Bougrad, and Jan Provoost, IMEC.
  Mar 24, 2008
  7   Low Power Design For Analog/Mixed-Signal IP   Navraj Nandra, Synopsys
  Mar 04, 2008
  8   Proportional-integral-derivative explained   Javier Gutirrez, National Instruments
  Apr 13, 2007
  9   Utilizing Clock-Gating Efficiency to Reduce Power   Mitch Dale, Calypto Design Systems
  Jan 15, 2008
  10   Multi-language Functional Verification Coverage for Multi-site Projects   Apurva Kalia, Cadence Design Systems
  Feb 18, 2008
  11   A New Approach to In-System Silicon Validation and Debug   Miron Abramovici and Paul Bradley, Dafca
  Sep 16, 2007
  12   Accellera VHDL Standard   Jim Lewis, SynthWorks VHDL Training
  Oct 25, 2007
  13   Getting Back to Basics with Planning, Metrics, and Management   Hamilton Carter, Cadence Design Systems
  Jul 13, 2007
  14   Practical Applications of Statistical Static Timing Analysis   Parveen Khurana and Michael Jacobs, Cadence Design Systems, Inc.
  Dec 18, 2006
  15   PCB Tools Vendors Reference Chart   Gabe Moretti
  Feb 14, 2008
  16   Multi-language Functional Verification Coverage for Multi-site Projects   Apurva Kalia, Cadence Design Systems
  Apr 12, 2008
  17   A Power Integrity Wall follows the Power Wall   Raj Nair, Anasim Corp.
  Apr 08, 2008
  18   The Great EDA Cover-up   Brian Bailey
  Nov 26, 2007
  19   Complex SoC Testing with a Core-Based DFT Strategy   Sandeep Kaushik, Synopsys and Paul Policke, Qualcomm
  Feb 26, 2008
  20   Power-Sensitive 65nm Designs Increase the Need for Transistor-Level Verification   Mike Demler, Synopsys, Inc.
  Aug 27, 2007
  21   What floorplan information is needed for synthesis   Jack Erickson, Cadence Design Systems
  Apr 22, 2008
  22   Signoff for Manufacturability   Chin-Chi Teng and Rahul Deokar, Cadence Design Systems, Inc
  Oct 08, 2007
  23   Host Bus Adapter (HBA) Verification with Trek   Adnan Hamid, Beker Verification Systems
  May 06, 2008
  24   Power Integrity and Energy Aware Floor Planning   Raj Nair and Donald Bennett, Anasim Corp
  Jan 29, 2008
  25   Why we need an analog design flow that's like digital now   Nelson Seiden, Knowlent Corporation
  Jan 07, 2008

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