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Scan compression reduces the amount of data needed for digital IC manufacturing tests, thereby lowering the cost of executing patterns on the tester. EDA solutions for implementing scan compression on-chip are readily available, but how do you measure compression performance among alternative vendor solutions to ensure a reliable, "apples-to-apples" comparison? There are a number of factors to consider. In this article, we focus on three fundamental performance metrics: fault coverage loss, pattern inflation, and area overhead. A closer look at each of these metrics is beneficial because each degrades compression performance and directly increases test costs at any level of compression.
The best way to compare performance is to use the compression ratio, defined as the ratio of the number of internally balanced scan chains to the number of scan channels (pairs of scan I/O pins), as the independent variable in your analysis. If your uncompressed design has 10 scan chains with 10 scan channels, then the compression ratio is 1:1. If you add compression so the number of internal scan chains is 100, then the compression ratio is now 10:1 or 10x.
Fault Coverage Loss from Compression
Fault coverage loss measures a compression tool's ability to accommodate unknown logic states without exhibiting a significant loss in fault coverage, and depends on the design and what type of test you are running. Coverage loss does not degrade compression performance per se; instead, it lowers the quality of test and increases test escapes. Even if the compression solution is fully "X-tolerant," fault coverage can still decrease at high compression levels if your design contains a very large number of unknowns.
Begin by generating a transition delay test for your scan design without adding any compression, and measure the testable fault coverage, defined as the ratio of detected faults to detectable faults in the uncollapsed fault list. Next, target the same design at several different compression ratios using the same ATPG constraints and settings as before. Since the compression circuits will not be tested directly on the ATE, you can exclude these faults in the ATPG runs.
Figure 1 shows the kind of flat characteristic you want to see: there is negligible loss in coverage at the higher compression levels. Be aware that fault coverage statistics can vary slightly from one tool to the next due to differences in fault accounting. Simply lowering a tool's maximum fault coverage target to compensate for these differences will always favor the tool with the highest reported fault coverage. This is because the most difficult-to-detect faults are near the end of the ATPG run — in the tail of the fault coverage convergence curve — where many more patterns are required to detect relatively fewer faults, so lowering the coverage target significantly reduces the number of patterns needed. Since it is often difficult to determine exactly how the fault lists differ, it is advisable when evaluating different compression solutions to create a single fault list with faults common to all ATPG tools.
1. Fault coverage loss measurement of a transition delay test produced by Synopsys' TetraMAX ATPG and DFT MAX Adaptive Scan solutions.
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