Verification
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High-level synthesis, verification and language
The preferred high-level design methodology proceeds from high-level code to RTL code. Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.
Facilitating at-speed test at the register transfer level
This white paper discusses at-speed testing challenges and discusses a solution for facilitating at-speed test at the register-transfer level.
Guidelines for complex SoC verification
As verification takes up a significant part of the design cycle, planning, managing the project dynamics and a metrics-driven execution will be of much help says the author, a senior ASIC engineer
Partitioning an ASIC design into multiple FPGAs
This article outlines the most common approaches and flows to consider before you embark on your next partitioning project. Ultimately, you can accelerate the verification phase by using an ASIC prototyping approach that allows you to build multi-FPGA based prototypes of ASIC designs in an intuitive fashion, with little or no modifications to the original design.
A formal methods-based verification approach to medical device software analysis
How to use formal methods"based abstract interpretation techniques to mathematically prove the absence of a defined set of run-time errors and a comparison with techniques as code review, static analysis, and dynamic testing.
Managing Complex SoC verification using plan based verification techniques
Meeting the quality requirements of a complex SoC requires managing large verification projects. In this article, Freescale and STMicroelectronics recount a recent experience with a verification management solution (Incisive Enterprise Manager) from Cadence, for the verification of a 32-bit microcontroller project for the automotive industry.
Researchers propose commonsense plan to improve verification process
Researchers have proposed an integrated, all-encompassing plan for verification teams based on a commonsense approach and proper documentation of all aspects of the process
Layering it on--a new approach to automating system tests
Here's a layered approach to testing that uses pluggable software components to assure scalability and portability.
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«March 2010 Verification
About the EDA Verification How-To Section
The EDA DesignLine's Verification How-To section delivers highly technical design articles focused on the automated tools used by verification engineers to verify a design.
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