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EDA DesignLine > Learning Center > Technical Paper Library

		Featured Technical Papers


		10 Ways to Reduce Cost in Outsourced Prototyping Screaming Circuits Synopsys Eclypse Low Power Solution Synopsys Interoperability Comes to EDA Tools Tanner Research

Technical Papers

Title	Author/Company	Published
Closing the Chip Architecture Implementation Feedback Loop	Cadence Design Systems	Jul 2009 Technical Paper
Eliminating Routing Congestion Issues with Logic Synthesis	Mike Clarke et al Cadence Design Systems	Jun 2009 White Paper
Modeling Parasitics in Sub-Micron IC Designs: Extract Them Before They Cost You a Re-Spin	Jeff Miller Tanner EDA	May 2009 Technical Paper
Design Tip: Simulating "Raw" Error Vector Magnitude (EVM) for a Quick Measure of a Circuit's EVM Performance	Agilent Technologies	May 2009 Technical Paper
Open Systems Speed Easy EDA Tool Integration: Adding ClioSoft DDM to Synopsys Custom Designer	Srinath Anantharaman and Les Spruiell Cliosoft and Synopsys	Apr 2009 Technical Paper
The Next Generation in Test and Debug Solution—cJTAG - IEEE 1149.7	Pierre-Xavier Thomas IPextreme	Apr 2009 Technical Paper
Cornering Those Corner Case Bugs: Functional Coverage On Multiple Interfaces	Sharan Basappa HCL Technologies	Apr 2009 Technical Paper
Characterizing Custom Analog Blocks in Mixed-Signal Microcontrollers	Jay Jayakumar Luminary Micro	Mar 2009 White Paper
Optimization of OPC Runtime Using Efficient Optical Simulation	Mohamed Al-Imam and Walid A. Tawfic Mentor Graphics	Aug 21, 2008 Mentor Graphics Technical Library
Tolerable CD Variation Analyzer Using Perturbed Nominal Models Demonstrated on altPSM	Mohamed Al-Imam et al. Mentor Graphics	Aug 21, 2008 Mentor Graphics Technical Library
Safe Interpolation Distance for VT5 Resist Model	Walid Tawfic et al. Mentor Graphics	Aug 21, 2008 Mentor Graphics Technical Library
Reducing IC Cycle Time with Calibre	Mathew Hogan Mentor Graphics	Jul 28, 2008 Mentor Graphics Technical Library
The New Wave in Functional Verification: Intelligent Testbench Automation	Mark Olen Mentor Graphics	Jul 2008 Mentor Graphics Technical Library
Where Should I Use Formal Functional Verification?	Lawrence Loh Jasper Design Automation	Jul 2008 White Paper
Firmware Driven OVM Testbench	Jim Kenney Mentor Graphics	Jun 25, 2008 Mentor Graphics Technical Library

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		Most Popular Technical Papers
		1. How to Inexpensively Design an ASIC in 5 Weeks 2. Eliminating Routing Congestion Issues with Logic Synthesis 3. Multi-Voltage Design Flow with Olympus-SoC 4. FPGA Design Methods for Fast Turn Around 5. Closing the Chip Architecture Implementation Feedback Loop MORE


		Highest Rated Technical Papers
		1. VLSI Implementation of CS-ACELP Vocoder Algorithm 2. The Value of Combining Processor-Driven Testbenches with Traditional HDL Testbenches 3. Electronic Systems Prototyping: Tools and Methodologies for Better Observability 4. PID Without a PhD 5. Fantastic Failures MORE

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Accenture seeking Project Management Team Lead in Charlotte, NC

Accenture seeking Software Engineer in Salt Lake City, UT

Boeing Company seeking Software Engineer in Herndon, VA

Switch and Data seeking Customer Solutions Engineer in Dallas, TX

Chart Industries seeking Sr. Developer in Cleveland, OH



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