| |
Green Engineering—Improving the Environment and the Bottom Line
|
|
National Instruments
|
|
Jun 06, 2008
White Paper
|
| |
Top-Down SoC Floor Planning with Re-Use
|
|
ChipEDA
|
|
2008
White Paper
|
| |
Path Tracing: An Intelligent Verification Technology for Simulation-Based Environments
|
|
Nusym
|
|
May 2008
White Paper
|
| |
Increasing Productivity With Quartus II Incremental Compilation
|
|
Altera
|
|
May 2008
White Paper
|
| |
Novel Method for Optimizing Lithography Exposure Conditions Using Full-Chip Post-OPC Simulation
|
|
John Sturtevant et al.
Mentor Graphics
|
|
Apr 14, 2008
Mentor Graphics Technical Library
|
| |
OPC Model Calibration Considerations for Data Variance
|
|
Mohamed Bahnas and Mohamed Al-Imam
Mentor Graphics
|
|
Apr 14, 2008
Mentor Graphics Technical Library
|
| |
Advanced Debug Methods for DSM Driven Testbenches
|
|
Jim Kenney
Mentor Graphics
|
|
Apr 2008
ARM IQ Article
|
| |
Designing RF, Analog and Digital on PCB
|
|
John Isaac
Mentor Graphics
|
|
Mar 28, 2008
Mentor Graphics Technical Library
|
| |
Preserving Freedom of Choice When Designing FPGAs
|
|
Ehab Mohsen
Mentor Graphics
|
|
Mar 28, 2008
Mentor Graphics Technical Library
|
| |
The Use of Advanced Verification Methods to Address DO-254 Design Assurance
|
|
James P. Keithan et al.
Mentor Graphics and XtremeEDA
|
|
Mar 20, 2008
Mentor Graphics Technical Library
|
| |
Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
|
|
Michelle Lange and Tom Dewey
Mentor Graphics
|
|
Mar 20, 2008
Mentor Graphics Technical Library
|
| |
Stator Coupling Model Analysis
|
|
Johan Ihsan Mahmood
Avago
|
|
Mar 13, 2008
White Paper
|
| |
Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification
|
|
Real Intent and Sunburst
|
|
2008
White Paper
|
| |
The Next Generation of Source Code Analysis
|
|
Gwyn Fisher
Klocwork
|
|
Feb 2008
White Paper
|
| |
Designing Drop-in Pseudo-Static Memories
|
|
Jarrod Eliason
Ramtron
|
|
Feb 2008
White Paper
|
| |
Bottom-Up Design Flow Using Precision Synthesis
|
|
Shantuna Kamat
Mentor Graphics
|
|
Nov 28, 2007
Mentor Graphics Technical Library
|
| |
Comprehensive Verification of ARM Processor-Based SoC Designs
|
|
Amjad Qureshi and John Brennan
Cadence
|
|
Nov 2007
ARM IQ Article
|
| |
A Fully Automated High Performance Implementation of ARM Cortex-A8
|
|
Stuart Riches et al.
ARM and Magma Design Automation
|
|
Nov 2007
ARM IQ Article
|
| |
Minimizing the Cost of Using Free Processor IP
|
|
Darren Zacher
Mentor Graphics
|
|
Nov 02, 2007
Mentor Graphics Technical Library
|
| |
Applying Assertion-Based Formal Verification to Verification Hot Spots
|
|
Ping Yeung and Sundaram Subramanian
Mentor Grapics
|
|
Oct 25, 2007
Mentor Graphics Technical Library
|
| |
A Comparison of Metastability Modeling Methods
|
|
Chris Kwok and Roger Sabbagh
Mentor Graphics
|
|
Oct 24, 2007
Mentor Graphics Technical Library
|
| |
SPIRIT IP-XACT Controlled Design Flow Applied on a High Level Communication Synthesis
|
|
Emmanuel Vaumorin et al
Magillem Design Services and OFFIS
|
|
Oct 2007
White Paper
|
| |
Introduction to Algorithmic Test Generation
|
|
Cliff Lyons and Mark Olen
Mentor Graphics
|
|
Oct 15, 2007
Mentor Graphics Technical Library
|
| |
Managing Functional Verification Projects: Meeting the Challenges of High-Level Verification in Today's SoCs
|
|
Kwamina Ewusie and Rajat Mohan
Synopsys
|
|
Oct 2007
White Paper
|
| |
Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation
|
|
Erica Brand
Cadence
|
|
Sep 2007
White Paper
|
