|
Rank |
|
Title |
|
Author/Company |
|
Date/Type |
| |
1
|
|
Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification
|
|
Real Intent and Sunburst
| |
Mar 13, 2008
White Paper |
| |
2
|
|
Managing Functional Verification Projects: Meeting the Challenges of High-Level Verification in Today's SoCs
|
|
Kwamina Ewusie and Rajat Mohan
Synopsys
| |
May 21, 2008
White Paper |
| |
3
|
|
Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions
|
|
Mark Litterick
Verilab
| |
Jun 10, 2008
White Paper |
| |
4
|
|
Path Tracing: An Intelligent Verification Technology for Simulation-Based Environments
|
|
Nusym
| |
May 23, 2008
White Paper |
| |
5
|
|
Top-Down SoC Floor Planning with Re-Use
|
|
ChipEDA
| |
May 27, 2008
White Paper |
| |
6
|
|
Advanced Debug Methods for DSM Driven Testbenches
|
|
Jim Kenney
Mentor Graphics
| |
Jun 11, 2008
ARM IQ Article |
| |
7
|
|
Increasing Productivity With Quartus II Incremental Compilation
|
|
Altera
| |
Jun 25, 2008
White Paper |
| |
8
|
|
ZeBu: A Unified Verification Approach for Hardware Designers and Embedded Software Developers
|
|
Emulation and Verification Engineering (EVE)
| |
Mar 14, 2007
White Paper |
| |
9
|
|
Designing RF, Analog and Digital on PCB
|
|
John Isaac
Mentor Graphics
| |
Apr 14, 2008
Mentor Graphics Technical Library |
| |
10
|
|
Stator Coupling Model Analysis
|
|
Johan Ihsan Mahmood
Avago
| |
Jun 09, 2008
White Paper |
| |
11
|
|
Green Engineering—Improving the Environment and the Bottom Line
|
|
National Instruments
| |
Jun 09, 2008
White Paper |
| |
12
|
|
A Fully Automated High Performance Implementation of ARM Cortex-A8
|
|
Stuart Riches et al.
ARM and Magma Design Automation
| |
Dec 13, 2007
ARM IQ Article |
| |
13
|
|
Applying Assertion-Based Formal Verification to Verification Hot Spots
|
|
Ping Yeung and Sundaram Subramanian
Mentor Grapics
| |
Nov 01, 2007
Mentor Graphics Technical Library |
| |
14
|
|
Introduction to Algorithmic Test Generation
|
|
Cliff Lyons and Mark Olen
Mentor Graphics
| |
Nov 01, 2007
Mentor Graphics Technical Library |
| |
15
|
|
Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Reference Verification Methodology (RVM)
|
|
Charles Li and Ashesh Doshi
Synopsys
| |
Aug 04, 2005
Product Paper |
| |
16
|
|
Introduction to CPLD and FPGA Design
|
|
Bob Zeidman
Zeidman Consulting
| |
Jun 05, 2006
2004 Embedded Systems Conference |
| |
17
|
|
Comprehensive Verification of ARM Processor-Based SoC Designs
|
|
Amjad Qureshi and John Brennan
Cadence
| |
Dec 13, 2007
ARM IQ Article |
| |
18
|
|
Demystifying DO-254
|
|
Tom Dewey
Mentor Graphics
| |
Mar 10, 2008
Mentor Graphics Technical Library |
| |
19
|
|
Designing Drop-in Pseudo-Static Memories
|
|
Jarrod Eliason
Ramtron
| |
Mar 13, 2008
White Paper |
| |
20
|
|
Computation of parasitic capacitances of an IC cell in accounting for photolithography effect
|
|
Zhuoxiang Ren, Weidong Zhang, and Jim Falbo
Mentor Graphics
| |
Jun 30, 2006
Mentor Graphics Technical Library |
| |
21
|
|
An ESL Methodology for Functional Verification between Untimed C++ and RTL using SystemC
|
|
David Burnette
Mentor Graphics
| |
Nov 27, 2006
Mentor Graphics Technical Library |
| |
22
|
|
The Next Generation of Source Code Analysis
|
|
Gwyn Fisher
Klocwork
| |
Feb 08, 2008
White Paper |
| |
23
|
|
Comparison of Eye Patterns Generated By Synopsys HSPICE and the Agilent PLTS
|
|
Samtec
| |
Nov 16, 2005
Technology Paper |
| |
24
|
|
Bottom-Up Design Flow Using Precision Synthesis
|
|
Shantuna Kamat
Mentor Graphics
| |
Dec 05, 2007
Mentor Graphics Technical Library |
| |
25
|
|
Novel Method for Optimizing Lithography Exposure Conditions Using Full-Chip Post-OPC Simulation
|
|
John Sturtevant et al.
Mentor Graphics
| |
May 15, 2008
Mentor Graphics Technical Library |
