|
Score |
|
Title |
|
Author/Company |
|
Date/Type |
| |
5
|
|
VLSI Implementation of CS-ACELP Vocoder Algorithm
|
|
G. Sudharsana
College of Engineering, Guindy
| |
Mar 31, 2006
White Paper |
| |
4.75
|
|
The Value of Combining Processor-Driven Testbenches with Traditional HDL Testbenches
|
|
Jim Kenney
Mentor Graphics
| |
Apr 28, 2006
Mentor Graphics Technical Library |
| |
4.62
|
|
Electronic Systems Prototyping: Tools and Methodologies for Better Observability
|
|
Frederic Leens
Byte Paradigm
| |
Nov 28, 2005
Technology Paper |
| |
4.5
|
|
Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification
|
|
Real Intent and Sunburst
| |
Mar 13, 2008
White Paper |
| |
4.44
|
|
Multi-Threaded Design Tackles SoC Performance Bottlenecks
|
|
Elchanan Rushinek and Pete Del Vecchio
Mobileye Vision Technologies and MIPS Technologies
| |
Nov 20, 2006
White Paper |
| |
4.44
|
|
Fantastic Failures
|
|
Kim Fowler
| |
May 09, 2006
2005 Embedded Systems Conference |
| |
4.4
|
|
Implementing an End-to-End Low-Power Multi-Voltage Methodology
|
|
Synopsys
| |
Nov 09, 2007
White Paper |
| |
4.4
|
|
SVA@Interface (For SATA Link, Application Layer interface)
|
|
HCL Technologies
| |
Aug 28, 2006
White Paper |
| |
4.33
|
|
Active Noise Regulation
|
|
Raj Nair and Donald Bennett
ComLSI
| |
Jan 18, 2007
White Paper |
| |
4.25
|
|
Delay-Safe False Paths
|
|
FishTail Design Automation
| |
May 17, 2007
White Paper |
| |
4.25
|
|
Cat 5 Cable Modeling for DVI/HDMI links
|
|
Donald Bennett and Raj Nair
ComLSI
| |
Dec 20, 2006
White Paper |
| |
4.21
|
|
Program SPI Flash In-Circuit via JTAG
|
|
Rick Folea
Ricreations
| |
Nov 14, 2005
Product Paper |
| |
4.2
|
|
Effective Stackup Design for High-speed Interfaces
|
|
Mentor Graphics
| |
Feb 12, 2007
Mentor Graphics Technical Library |
| |
4.18
|
|
Designing an RF System-In-Package with Improved IC Design Environment
|
|
Mathieu Behaghel
STMicroelectronics
| |
May 01, 2007
Mentor Graphics Technical Library |
| |
4.18
|
|
A Practical Guide to High-Speed Printed-Circuit-Board Layout
|
|
John Ardizzoni
Analog Devices
| |
Sep 16, 2005
Analog Dialogue Article |
| |
4.17
|
|
Maximizing Team Productivity through Efficient Design Data Management
|
|
Paul Beard and Srinath Anantharaman
AMCC and ClioSoft
| |
Nov 07, 2006
White Paper |
| |
4.08
|
|
True DSP Synthesis: The Birth of a New Design Methodology
|
|
Chris Eddington
Synplicity
| |
Nov 14, 2005
Product Paper |
| |
4.07
|
|
High Performance FPGA Designs
|
|
Kartik Subramanian Iyer and Nusrat Ali
HCL Technologies
| |
Nov 16, 2006
White Paper |
| |
4.06
|
|
Introduction to Verilog
|
|
Bob Zeidman
Zeidman Consulting
| |
Jun 01, 2006
2004 Embedded Systems Conference |
| |
4
|
|
Using FPGAs as Coprocessors for DSP and Image Processing
|
|
Dave Pellerin
Impulse Accelerated Technologies
| |
Apr 27, 2007
2007 Embedded Systems Conference |
| |
4
|
|
Memory Management: Part 1
|
|
Niall Murphy
Panelsoft
| |
May 09, 2006
2005 Embedded Systems Conference |
| |
4
|
|
Tips for Using Synplify Pro to Improve Altera Device Performance
|
|
Gael Paul
Synplicity
| |
Mar 31, 2006
Product Paper |
| |
4
|
|
Overview of LabVIEW for Everyone
|
|
Jeffrey Travis
| |
Nov 14, 2005
Book Chapter |
| |
3.93
|
|
HDL Simulation and Mathematical Modeling Integration
|
|
Adam Milik and Adam Zytka
Aldec
| |
May 11, 2006
Technical Paper |
| |
3.91
|
|
How Chips Are Designed
|
|
Jim Turley
| |
Nov 15, 2005
Book Chapter |
