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| On-Demand Webinars Archive |
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Event |
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Date/Time |
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Length |
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Co-simulation Enables Efficient Co-Design of WLAN Antenna and Circuitry
Agilent Technologies |
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May 28, 2008 |
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60 min. |
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Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis
Apache Design Solutions |
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May 08, 2008 |
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60 min. |
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Selecting the Optimal Embedded Memory IP Architecture
Synopsys |
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May 01, 2008 |
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60 min. |
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Building a Configurable Gigabit Ethernet Subsystem for ComplexSystem-0n-Chips
Synopsys, Inc. |
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Dec 19, 2007 |
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60 min. |
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Co-Simulation with MATLAB® Simulink®. and HDL Simulators
The Mathworks |
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Dec 06, 2007 |
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60 min. |
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Manage Power at Each Design Stage with a Production-Proven, Holistic Solution to Low-Power Design
Cadence |
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Nov 06, 2007 |
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60 min. |
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Circuit-Simulation-Driven RF/Analog System-In-Package Design
Cadence |
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Sep 06, 2007 |
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60 min. |
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Connecting to DDR2: Mitigating High-Speed Challenges in SoC Designs
Synopsys |
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Jul 25, 2007 |
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90 min. |
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High-Speed Serial Interface Testing - Solving The Analog Test Problem With A Fast And Accurate Digital Solution
Synopsys |
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Jul 12, 2007 |
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60 min. |
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Accurate Verification of Next-Generation Custom Digital SoC and Memories in 65/45nm Technologies
Cadence |
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Jun 28, 2007 |
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60 min. |
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The Complete USB 2.0 IP Solution: Understanding Today's Design Considerations and Managing Tomorrow's Challenges
Synopsys |
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Jun 27, 2007 |
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60 min. |
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Verification of Next-Generation Mixed-Signal Communication SoC In 65/45nm Technologies
Cadence |
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Jun 21, 2007 |
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60 min. |
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A Structured Approach to Effective Verification Closure
Mentor Graphics |
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Jun 13, 2007 |
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60 min. |
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Validating of DDR/II/III Memory Designs
Agilent Technologies |
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May 30, 2007 |
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60 min. |
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