EDA News | News Source for EDA Tools, DFM, ESL, Verification, Chip, and System Design

CoWare, Xilinx team on LTE basestation design
ESL design software vendor CoWare Inc. and FPGA vendor Xilinx Inc. have signed an agreement under which CoWare is integrating and distributing models of Xilinx's LTE baseband IP portfolio with its SPW LTE solution.

Synopsys to acquire ESL vendor CoWare
EDA and IP vendor Synopsys announced its second major acquisition in two weeks, saying it signed a definitive agreement to acquire electronic system-level design software vendor Coware. Financial terms of the agreement were not disclosed.

Hardware Testing
Board testing is harder than you think, but there are solutions

An analyst's 10 reasons to be cheerful
Bill McClean, analyst with IC Insights Inc. (Scottsdale, Ariz.) has provided ten reasons that support the idea that 2010 could be between a good and a great year for the semiconductor industry.

New CEO Sandeep Vij forms 'Team MIPS'
Signing Sandeep Vij as its new CEO may turn out to be just what MIPS Technologies needed, as the world's number two processor IP company struggles to steal the spotlight back from ARM -- both in media attention and the industry's mindshare.

"Also of Interest" and "Elementals" for February 8, 2010; plus recent "Planet Analog" Newsletters
Check out these interesting and tutorial items from other engineering and design publications, courtesy of Planet Analog, as well as an archive of the Planet Analog Newsletter

Cadence back in black in Q4
EDA vendor Cadence Design Systems Inc. (San Jose, Calif.) reported a net income of $2 million, based on generally accepted accounting principles (GAAP), for the fourth quarter of 2009, compared to a net loss of $1.63 billion a year ago.

Universities gain access to Agilent, EVE, Altium, Evatronix tools
This week, EDA companies EVE SA, Agilent Technologies Inc., Altium Ltd. and Evatronix SA have either signed sales contracts or collaboration agreements to provide global universities with their tools.

Virage Logic posts strong growth
Virage Logic Corp. posted sales of $21.7 million for the first quarter of fiscal year 2010, ended Dec. 31, 2009, up from $11.3 million a year ago.

DRAM leads top ten IC growth sectors for 2010, says analyst
All but four of about 28 IC product categories will grow in 2010 resulting in an overall IC market growth of 15 percent, according to a forecast from market research firm IC Insights Inc. (Scottsdale, Ariz.).

NEWS: Restructuring starts to pay dividends for Enea
A year that has been characterized by cost cutting and restructuring programs has seen Enea (Stockholm, Sweden) report its year-end results with net sales falling by 15 percent, mainly due to reduced royalties from telecom customers and a downturn in the demand for consultancy services.

Synopsys buys virtual system prototyping provider
EDA and IP vendor Synopsys has acquired virtual system prototyping technology provider Vast Systems Technology. Financial terms of the deal were not disclosed.

Arrgghh! My FPGA's not working: Problems with the RTL
We all tend to have high levels of faith in various aspects of the FPGA design flow, but it's not long before we discover how unfounded this faith can be. In reality, bugs can manifest themselves in any portion of the FPGA design flow.

University of Wisconsin students use Altium Designer
Australian design tool provider Altium said undergraduate students at the University of Wisconsin's College of Engineering will use Altium Designer to develop foundations in modeling, characterization and application of semiconductor devices.

ARM lays out roadmap with three more cores
ARM Holdings plans to launch three processor cores during 2010. The cores, codenamed Eagle, Heron and Merlin, all have lead licensing customers and deliveries of intellectual property will start either in 2010 or early in 2011 depending on the core, said ARM CEO Warren East.

About the EDA DesignLine News Section
About the EDA DesignLine News Section News/analysis source for engineers tapping EDA tools/techniques for issues such as chip design, SoC architectures, electronic system level (ESL) design, DFM/DFY design, functional/physical verification, FPGA, PLD, analog, and mixed-signal design.