Systemwide I/O planning is an exercise in coordinating device placement with associated pin and net assignments across the chip-package-board system to maximize system quality for the target application. Achieving this goal is a multidomain balancing act of trade-offs and iterations.
What might be the ideal pad ring layout from a chip perspective may be less than ideal from a package routing or manufacturing perspective. The package ball pad assignment that minimizes layer count at the board level might prove inadequate from the standpoint of chip-level power distribution.
The key to systemwide I/O planning is achieving balance across all domains of the system so key design criteria can be weighed and evaluated in full system context to guide design decisions.
Attempting any type of coordinated design planning across the chip, package and board using traditional tools and serial methodologies can be frustrating at best. One problem is separate design environments and databases--one for the chip, a second one for the package, and a third for the board. Even in this situation, it's not uncommon for design teams to collaborate using spreadsheets to communicate pin assignments. The shortcoming is that it is based on snapshots of static data, resulting in a highly iterative, error-prone process that does little to reduce cycle time or cost of results.
Device integration at the package level in the form of System-in-Package (SiP), stacked-die and Package-on-Package (PoP) further challenge traditional tools and methodologies. The multichip aspect of these packages adds the dynamic of chip-to-chip connectivity in addition to chip-to-package. Designers often use the fixed I/O of one chip to influence I/O and connectivity assignments on adjacent chips.
While chip floor planning and implementation tools work well for their intended application, they lack the ability to deal with multiple chips simultaneously. On the other hand, package- and board-level tools that support multiple chips lack the needed gate and macro visibility necessary for chip-level I/O placement and assignment.
Several other factors and considerations figure into the systemwide I/O planning puzzle. Some are well known, such as system compatibility, completeness and availability of IP and package lead times; but there are other, more oblique, factors. Designing for application-specific packaging, detecting and resolving differences between logical and physical data, and correlating data across domains are just a few examples.
Serial approaches
The historic approach to chip-package-board design has been a serial top-down flow where the chip drives package connectivity and, in turn, the package drives board connectivity. Increasingly, there are situations requiring compatibility with existing systems where the board becomes the influencing factor driving upstream connectivity through the package and back into the chip. This bottom-up approach necessitates some element of package design to derive the starting point for pad ring layout on the chip. This is especially true for flip-chip packaging, where a high degree of coordination is necessary to derive a bump pattern that is mutually conducive to route both chips and packages.
During feasibility studies or early-stage design planning, it's not uncommon for design decisions to be made in the absence of detailed information. An example is the availability and completeness of silicon intellectual property (IP). In many cases, IP isn't available during early stages because it is not yet designed or purchased. Therefore, a placeholder is inserted that approximates the size and pin count so feasibility or planning can proceed. Effective systemwide I/O planning requires the flexibility to instantiate missing data on-the-fly, work at different levels of abstraction, and use best available data.
Success or failure for many consumer applications is determined by their ability to meet product introduction targets. In some cases, the schedule dictates the package is sent to manufacturing before chip completion, due to complexity of the package substrate and assembly processes. This requires a high degree of confidence in the chip and package working together, achieved only through coordinated design planning.
Another twist for I/O planning is the use of application-specific packaging in which one chip is designed into multiple package configurations depending on end-market applications. The challenge is to derive an I/O pad ring layout that works equally well for the range of configurations. Accomplishing this is a highly iterative, cumbersome process due to the "one die, one package" orientation of traditional tools and methodologies.
Once companies embark on a process for systemwide I/O planning, they're quickly confronted with the issue of syntactical differences in net names between domains. It's not uncommon for a logical net to be referred to by three different substrate-specific names. For example, the logical net for Address bit 0 may be called ADDR(0) on the chip, A(0) on the package and AD(0) on the board. From the system perspective, these are all the same net, but for I/O planning they must be correlated and mapped without changing their respective net lists.
