SystemVerilog gets boost from OVM

The OVM, based on IEEE Std. 1800TM - 2005 SystemVerilog standard, provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. As a joint development initiative between Mentor Graphics(r) and Cadence(r) Design Systems, the OVM is supported on multiple verification platforms ideally suited to both novice and expert verification engineers.

Distributed under the standard open-source Apache^TM 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge from www.ovmworld.org . The OVM Web site is the central point of access for the OVM source code, providing information about partners, events, seminars, training, how-to instructions and future plans.

The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable verification IP (VIP) in SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, and significantly shortens the time to create verification environments. It easily integrates plug-and-play VIP and ensures code portability and reuse.

Additional functionality is planned for release later in 2008. Cadence and Mentor have collaborated to ensure that the OVM runs on their simulators and enables backwards compatibility with their existing environments, Advanced Verification Methodology from Mentor Graphics, and Incisive(r) Plan-to-Closure Methodology (Universal Reuse Methodology module) from Cadence.

WEBINAR
1. Webinar 1: Verification of Complex Analog Designs

WEBINAR
2. Accurate Verification of Next-Generation Custom Digital SoC and Memories in 65/45nm Technologies

WEBINAR
3. Verification of Next-Generation Mixed-Signal Communication SoC In 65/45nm Technologies

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4. Webinar 3: Verification of Next-Generation Wireless SoC and Systems in Package