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Power management for chip design continues to be in the forefront, be it for optimization, analysis or verification. However, the power format battles have subsided and a single IEEE standard appears to be well on track.
2006 saw the rise of power format battles among electronic design automation (EDA) vendors, and users clearly indicated their preference by demanding an open and inclusive effort to create one standard. Magma, Mentor Graphics and Synopsys, with active support and participation from ARM, LSI, Infineon, Intel, Nokia, Nordic and Texas Instruments, donated, debated and, by February 2007, rapidly converged on Unified Power Format (UPF) under Accellera.
Using one shared example, eight vendors also demonstrated interoperability of their tools at last year's Design Automation Conference (DAC) in San Diego and clearly set the tone for "cooperate on formats, compete on tools." At the same time, the IEEE study group was approved to become a working group (P1801) to a standardize low-power format. Accellera, as its stated plan of action, donated UPF as a starting point for the P1801 Working Group.
Moving into 2008, we are about to see these efforts turn UPF into an IEEE Low-Power standard. The EDA vendors will enable UPF support in their mature, production-proven tools for verification, implementation and analysis. Designers will be able to specify their power requirements in this concise and universally accepted standard format, leading to better management of power-related design data and an evolution of improved methodologies.
Beyond the need for a single standard for a low-power format, the challenge is to successfully deploy this standard in every design flow. As we have learned from the past and the successful adoption of many standards, the ecosystem for the entire design flow must support the use of the standard. Through active participation in the IEEE P1801 Working Group, we have seen the influence on tool developers from intellectual property (IP) suppliers, library providers and leading designers. EDA vendors are working with aggressive schedules to show the reference flows in collaboration with foundries offering low-power processes. Additionally, various tutorials, technical papers and demonstrations have been presented at industry conferences, user group meetings and other private events. This helps to ensure that the designer community is aware of the standard and receives the necessary education for successful adoption.
The feverish pace of the IEEE group will bring us an improved format over Accellera's UPF 1.0. However, one must keep up with changing needs in response to technology advances, methodology enhancements and other business factors. Within the semiconductor industry, we did not focus on the growing power management issues until wireless communication and personal entertainment drove us to address it in a hurry.
By the end of 2008, all the collaborative hard work of the user and vendor representatives should result in better design tools and methodologies, and lead to green chips forever.
About the Author:
Yatin Trivedi , is the Director of Industry Partnership Programs at Magma Design Automation.
He can be reached at: yatin@magma-da.com
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