LONDON — Mentor Graphics is taking on an unspecified number of engineers from NXP Semiconductors' Design for Test operation and establishing an R&D facility in Hamburg , Germany, as part of a deal that also sees the chip maker adopting certain Mentor tools.
The arrangement also sees Mentor gaining rights to some of NXP's internally developed test tools.
NXP will start using Mentor's TestKompress compressed pattern generation tools and the YieldAssist failure diagnosis tools. It also provides interim support for NXP's test tools.
"NXP believes that a partnership with Mentor Graphics is the most effective way to continue to meet our manufacturing test needs and to deliver the highest quality devices to our customers," said Ren Penning de Vries, senior vice president and chief technical officer, NXP Semiconductors.
De Vries added NXP selected Mentor's technology for testing before tapeout and silicon to help improve time-to-market. "Our partnership allows NXP to use commercial DFT tools without disrupting any of our critical design projects."
"We are excited about our new business relationship with NXP. It not only brings new DFT technology to Mentor, but also brings the talent of world-class DFT developers which will help us accelerate the development and delivery of innovative DFT technologies into the marketplace," commented Joe Sawicki, vice president and general manager of the newly created Design-to-Silicon division at Mentor Graphics.
Separately, Mentor has aligned its integrated circuit implementation product lines under the Design-to-Silicon division so that, the company says, it can "better address the design and manufacturing challenges of 45-nm and smaller process nodes."
The division incorporates Mentor's IC products: the Olympus-SoC place-and-route system, the Calibre physical verification and DFM platform, and the design-for-test (DFT) product line.
