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The advent of handheld devices signaled an era of battery conservation. The demanding need of the consumer market to drive down the price of the handhelds called for the integration of several functions into a single gadget, and multiple applications running on a single gadget have put tremendous pressure on battery life. Power management is no longer an afterthought, but a necessity if these gadgets are to have any meaningful life as a mobile device.
Power management implies extra design effort. Design techniques have concentrated on conserving energy by allowing high-speed parts of the design to operate at higher voltages and frequencies and segmenting low-speed blocks to operate at lower voltages and frequencies. Of course, what is created must be verified. Power management design is therefore associated with increased verification effort.
Verification teams must come up with the right strategy for verifying low power designs to have even a prayer to complete verification of the critical functions in different power modes and have any measure of confidence that the design will work in the field. The fierce nature of competition in the consumer industry doesn't allow any extra time to complete the verification task. In fact, if anything, product development cycles are shrinking. A well-known fact of product development is that a bug that escapes detection at RTL will cost a lot more to fix downstream in the design cycle. A bug that is found in silicon is extremely expensive from not just a cost point of view, but also in terms of missed market windows and lost opportunities.
Verification techniques that focus solely on dynamic methods are expensive to set up and complete and require the development of a large and repeatable infrastructure. Developing and debugging testbenches is time consuming. Static checks offer an excellent alternative because they don't require the set-up time involved with dynamic verification techniques. They can pipe-clean a design to a great extent and find bugs rapidly.
Static checks for power management have traditionally focused on the gate and transistor level. While these are good checks to ensure that the implementation tools are behaving, they do not proactively verify a design when they should. Static checks run at RTL reduce the risk of failures and do so cost-effectively. Examples of bugs that can be found early in the design cycle are architectural and micro-architectural issues that need immediate attention. Critical signals like clocks and resets need to be checked for proper operation based on the power intent specified for a design. A failed reset resulting from a reset signal originating from a power domain that can be turned off is enough to render the chip dead on arrival. Static checkers developed for architectural and micro-architectural checks at the RTL will easily detect such issues.
Static checkers can augment and reduce the overall verification effort when designed intelligently. They can also act as a persistent check across various stages of design. Verification engineers can weed out design problems early on in the design cycle using static checks at RTL. Certainly then, static checks at RTL are indispensable to a robust verification methodology for power management. After all, a stitch at RTL will save nine in silicon.
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