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MANHASSET, NY — Oasys Design Systems came out of a five-year stealth mode to take the wraps off RealTime Designer, a design tool for physical RTL synthesis of 100-million-gate designs.
The tool is capable of synthesizing RTL to placed gates in a single pass and in a fraction of the time compared to traditional synthesis, according to the company.
Oasys claimed that traditional logic synthesis is running out of steam on designs of 20 million gates or larger. Synthesis is done a block at a time and without the context of the chip's floorplan. This approach typically leads to numerous iterations between synthesis and layout and suboptimal results in layout, according to Oasys.
RealTime Designer follows a "Place First" methodology that takes the RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement.
Chip-level constraints are automatically propagated across the blocks and the design is optimized by repartitioning it at the RTL and re-implementing until the chip-level constraints are met.
Usually, design teams must manually check for many results, such as design congestion, and send the design repeatedly through synthesis and layout.
RealTime Designer automates that process. Designers can give RealTime Designer the chip floorplan as input or, if no floorplan exists then Oasys will create a floorplan including macro, pin and I/O placement. At completion RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.
Oasys claimed that RealTime Designer completed synthesizing a physical block using TSMC 65nm technology in just 20 minutes and achieved design closure after a single iteration in place and route. In the traditional approach on the same design, a single iteration of synthesis took 14 hours.
According to Oasys, RealTime Designer is already in use in production flows at leading-edge semiconductor and systems companies worldwide.
"We are planning to expand the use of RealTime Designer in both our customer SoC flow, as well as for our own LSI designs," said Yoshio Inoue, Chief Engineer of Design Technology Division, Renesas Technology Corp.
Real Time Designer takes in standard inputs, including Verilog, standard timing and physical libraries, SDC timing constraints, and floorplan. VHDL will be available later this year.
RealTime Designer is immediately available and pricing begins at $395,000 for a one-year time-based license.
Oasys Design Systems is a privately funded company founded in 2004 that has EDA industry veterans on its board of directors.
Sanjiv Kaul, with 25-year EDA industry experience, was a Synopsys executive responsible for helping expand its RTL synthesis franchise to leadership in RTL to GDSII.
Joe Costello, Chairman and CEO Orb Networks, was president and chief executive officer at Cadence Design Systems, Inc., for more than a decade.
Larry Yoshida, Chairman and CEO Premier Technologies,
a veteran of almost two decades at Tokyo Electron, Inc. (TEL), introduces high-tech ventures and their technology offerings into Japan.
Johnson Limqueco, co-founder Vice-President of Research and Development of Oasys, was an Engineering Group Director at Cadence Design Systems, managing the physical synthesis team of SOC Encounter.
Oasys co-founder Paul van Besouw is president and CEO. He was responsible for managing the synthesis and physical synthesis teams at Cadence.
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