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Mentor Graphics joins SOI consortium





EDA DesignLine

PARIS — The silicon-on-insulator (SOI) Industry Consortium announced that Mentor Graphics Corp. has joined the organization.

By joining the consortium, Mentor Graphics (Wilsonville, Ore.) said it aims at expanding EDA tool and methodology support for the SOI technology. More specifically, Mentor said it will work on advancing design automation support for SOI-based products and systems in collaboration with other members.

"As we engage our expertise in modeling, characterization, analytics and constructive design tools with the needs of the global SOI user community, we can help designers and manufacturers exploit all of the underlying goodness of SOI technology," commented Robert Hum, VP and GM, Deep Submicron Technologies at Mentor Graphics.

Formed in 2007, the SOI consortium aims at accelerating the SOI technology and promoting its benefits in the market.

The founding membership in the group includes AMD, ARM, Cadence Design Systems, CEA-Leti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, NXP, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Synopsys, TSMC and UMC.

 






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