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Cadence Design Systems, Inc. announced a set of new design products and capabilities for faster production of digital system-on-chip (SoC) designs. According to Mike McAweeney, vice president of DFM marketing at Cadence, these new capabilities provide "what you design is what you get" (WYDIWYG) modeling and optimization for critical manufacturing variations during the design phase. This results in a manufacturing-intelligent physical implementation and signoff capability that correlates to foundry signoff.
Cadence will exhibit its 45nm design flows to semiconductor designers and design managers starting today at the CDNLive! Silicon Valley user conference. Production delivery is scheduled for the 7.1 release of Cadence Encounter® digital IC platform in October.
A standard IC design consideration has long been manufacturing variability, which can result in both catastrophic and parametric yield failures. Traditionally, these failures were avoided through "physical design rules," which prevented the implementation flow from creating any structures deemed risky. However, at advanced technology nodes of 65nm and especially at 45nm and below, the necessary "rules" are so conservative as to significantly limit IC performance and unnecessarily increase die area -- and still may not avoid all problems.
Cadence is directly modeling critical elements of the manufacturing process -- lithography, chemical mechanical polishing (CMP), and random variation -- and using the models to produce a DFM-correct design through a prevention, analysis and optimization sequence.
To prevent lithography violations in SoC applications, the Cadence NanoRoute® router adds new technology which avoids gross lithography errors during routing for an immediate reduction in lithographic "hotspots." Cadence Encounter QRC Extraction has been enhanced to support the advanced process models for accurate statistical parasitics extraction. For custom applications, a new capability of the Cadence Virtuoso® custom design platform leverages "recommended" rules as a starting point for further analysis and optimization. Accurate lithography analysis is accomplished using the Cadence Litho Physical Analyzer, formerly known as InShape from Clear Shape Technologies and recently acquired by Cadence. Any remaining lithography hotspots are optimized using a combination of grid- and space-based methods, the latter of which enables extremely fine-grained optimization and interconnect refinement.
The end result of this approach is a design which does not require excessive lithography correction during the photomask phase manufacturing -- it is essentially correct already. CMP and random variation are managed through similar approaches, using the new Cadence's CMP Predictor analysis, and optimized through intelligent metal-fill and currently multicorner timing optimization methods.
Cadence supports a suite of final analysis technologies that ensure the design will perform correctly after manufacturing. Critical lithography and CMP elements are analyzed using Cadence Litho Physical Analyzer and CMP Predictor. For timing analysis, Cadence is introducing a new statistical timing analysis system featured in the Cadence Encounter Timing System GXL.
Encounter Timing System GXL avoids the pessimism associated with "corners," many of which represent cases which are theoretically possible but increasingly unlikely. And second, Encounter Timing System GXL executes in a fraction of the time usually required to analyze timing on large sets of scenarios.
Cadence Litho Physical Analyzer, CMP Predictor, Cadence Encounter QRC Extraction and Encounter Timing System GXL are supported in foundry flows including the TSMC 8.0 Reference Flow.
In related news, Stratosphere Solutions, Inc., announced a collaboration with Cadence to increase 45nm semiconductor device yield by addressing a critical emerging challenge: manufacturing variability. The collaboration meets this challenge with improved process modeling, analysis and implementation flows that allow foundries, IDMs, ASIC and COT designers to increase the quality of their results.
The collaboration uses the new statistical timing analysis features in the Cadence Encounter® digital IC design platform in combination with variability models created by Stratosphere OzoneTM variability modeling environment to significantly improve process variation management, design performance, parametric yield and power consumption at advanced process geometries.
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