|
Venice, Florida — The MathWorks today announced it now offers a continuous verification workflow that connects system-level models and algorithms developed in MATLAB and Simulink with digital hardware simulators from the three major EDA companies. Designers and especially system architects, are often constrained in their task of developing and verifying a system level design by the limitations and ambiguities of the definition of "system" in Electronic System Level (ESL) market segment. Designers and architects must have the ability to integrate and verify an electronic subsystem with the rest od the system, which may consists of mechanical or other types of actuators and sensors, for example. MATLAB and Simulink, from The Mathworks, provide the needed functionality.
With the availability of EDA Simulator Link DS, which supports cosimulation between MATLAB and Simulink and the Synopsys VCS MX functional verification solution, The MathWorks completes its EDA Simulator Link portfolio. The first product in the family, the EDA Simulator Link MQ (for Mentor Graphics' ModelSim and Questa) was introduced in 2004, followed two years later by the EDA Simulator Link IN (for Cadence Incisive Simulator).
1. The total system running on Simulink, uses a simulator by another EDA vendor to co-simulate with the Device Under Test, written in a HDL.
EDA Simulator Link products from The MathWorks offer support for VHDL, Verilog, and mixed-language simulators, enabling engineers to connect MATLAB and Simulink to their choice of hardware description language (HDL) and register transfer level (RTL) simulator for their hardware design and verification tasks. The products also work seamlessly with Simulink HDL Coder from The MathWorks to automate integration of legacy RTL IP with designs developed in MATLAB and Simulink. The EDA Simulator Link products support design teams across FPGA and ASIC markets that are striving to reduce development time, design flaws, and verification costs.
The success of EDA Simulator Link products in improving product quality and cutting verification time has fueled demand for additional interfaces to hardware workflows. As a result, the EDA Simulator Link portfolio has expanded and has prompted EDA vendors to deliver similar tools for analog and mixed-signal simulators such as Synopsys Discovery AMS and Saber, Cadence Virtuoso Multi-Mode Simulation, Cadence PSpice and Cadence Allegro AMS Simulator, and Mentor Graphics ADVance MS (ADMS).
Key Features in EDA Simulator Link DS
EDA Simulator Link DS lets design, verification, and system engineers use MATLAB and Simulink to efficiently model, analyze, and verify HDL and RTL implementations. Key features include:
- Full VHDL, Verilog, and mixed-language cosimulation support
- MATLAB test bench capability, enabling the use of MATLAB code to stimulate HDL code and check its response
- MATLAB component capability, enabling simulation of MATLAB code in place of entities not yet coded in HDL
- User-selectable shared-memory and TCP/IP-socket communications modes
- Interactive or batch mode cosimulation, debugging, testing, and verification of HDL
EDA Simulator Link DS is available immediately. U.S. list prices start at $2,000.
|
