Editor"s Note: See also the related "How To" design article: Strategies for minimizing Xilinx implementation tool runtimes. In this article, author Philippe Garrault presents a variety of strategies which – when coupled with the new capabilities provided by the Xilinx ISE Design Suite 10.1 – can significantly reduce implementation tool runtimes.
Today, FPGA design is as sophisticated as any fixed-architecture implementation alternative, with gate counts and manufacturing processes pushing the leading edge. No longer are FPGAs considered only a scaled-back prototyping platform; today"s multi-million-gate devices offered at competitive price-points are fully capable of powering high-performance, high-volume products. Combined with their traditional benefits of extreme flexibility and programmability, as well ease-of-design, FPGAs are, in many cases, the best option for a wide variety of demanding, cost-sensitive and dynamic applications in computer, communications, consumer and automotive markets. So it is imperative that FPGA design tool environments keep pace with the device capabilities for which they are targeted.
The folks at Xilinx have introduced version 10.1 of their ISE Design Suite. This is a single unified release providing FPGA logic designers, embedded designers, and DSP designers with immediate access to the company"s entire line of design tools with full interoperability.
The ISE Design Suite 10.1 delivers significantly faster implementations with an average of 2X faster run times than its predecessor, thereby allowing designers to complete more turns per day.
SmartXplorer technology
Significant to this new release is the introduction of SmartXplorer technology, developed specifically to address the top challenges of the design community – timing-closure and productivity.
SmartXplorer technology addresses timing-closure and productivity issues.
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SmartXplorer technology leverages distributed processing across multiple Linux machines to enable even more implementation runs per day, and up to 38 percent faster performance by leveraging distributed processing and multiple implementation strategies. SmartXplorer technology also provides tools that allow users to monitor each run with individual timing reports.
PlanAhead Lite and strategy-based implementation
With the availability of the PlanAhead Lite tool in ISE Foundation software, users have access to a subset of the powerful floorplanning and analysis capabilities of the PlanAhead design and analysis tool. Included at no additional cost, PlanAhead Lite features PinAhead technology, an intuitive solution designed to simplify the complexities of managing the interface between the target FPGA and PCB.
PinAhead technology simplifies the complexities of managing the FPGA-PCB interface.
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PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout-related changes that typically happen downstream by performing design rule checks during interactive pin placement. Once the pin assignments have been completed, PinAhead provides the ability to export I/O port information through either comma separated value (CSV) files or via VHDL or Verilog headers.
With ISE Design Suite10.1, Xilinx has also simplified the process of determining optimal implementation settings. Designers now have the ability to specify and set their own unique design goals, whether they are working to maximize performance, optimize device utilization, reduce dynamic power, or minimize implementation time. For example, designers using the area reduction strategy can realize an average of 10 percent better logic utilization.
Improved verification
The ISE Design Suite 10.1 also benefits from the efforts of the company"s joint collaboration with Mentor Graphics. Through the use of IEEE IP encrypted models, ISE Design Suite 10.1 offers up to 2X faster run times. The new performance optimized BRAM, DSP, and FIFO simulation models further reduce RTL simulation run times by an additional 2X.
Second-generation XPower
Industry studies show that meeting power budgets is a growing challenge for FPGA designers, especially as process geometries continue to shrink. The ISE Design Suite 10.1 provides capabilities for users to analyze power requirements early in the design and optimize dynamic power throughout the design process.
XPower allows users to analyze power in terms of blocks, hierarchy, power rails, and resources used.
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The second generation XPower power analysis tool enhances power estimation by providing an improved user interface to make it easy to analyze power by blocks, hierarchy, power rails and resources used. Information is presented in both text and HTML report formats.
In addition to power analysis, ISE Design Suite 10.1 provides power optimization that"s both convenient and extensive. Using the integrated Power Optimization design goal feature, users have a simple, one-step process to specify power optimization. Combined with improvements in the map and place-and-route algorithms, users can reduce dynamic power in their designs by an average of 10 percent for 65 nm Virtex-5 devices and an average of 12 percent with Spartan-3 generation FPGAs.
Embedded and DSP tool integration
To help users achieve optimal embedded and DSP design results more quickly, ISE Design Suite 10.1 also introduces many ease-of-use enhancements to both the Xilinx embedded and DSP tools, including unified interoperability, which allows users to easily add System Generator modules within the ISE Project Navigator. Inter-tool integration enhancements between EDK and System Generator for DSP technologies enable more sophisticated FPGA SoC design incorporating both embedded and signal processing.
Availability and pricing
The ISE Design Suite 10.1 consists of ISE Foundation, Embedded Development Kit (EDK) with Platform Studio (XPS), System Generator for DSP, AccelDSP synthesis tool, ChipScope Pro analyzer and ChipScope Pro Serial I/O toolkit, PlanAhead design and analysis tool, and ISE simulator.
Users can install domain-specific DSP, embedded, and logic design products from either a DVD or electronic download. Using an electronic fulfillment process as the primary product delivery method provides users with access to not only the products they are entitled to, but evaluation versions of other Xilinx design tools.
All products in the ISE Design Suite 10.1 are immediately available with prices ranging from US$495 to $2,495. Full-featured 60-day evaluation versions can be downloaded from the Xilinx web site at no charge. For more information on the ISE Design Suite 10.1, visit www.xilinx.com/ISE.
