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Venice, Florida — CEVA, Inc. has introduced its next generation DSP subsystem platforms for developers using the CEVA-X family of DSP cores. The solutions offer a verified approach for efficiently integrating its cores into complex system on chips (SoCs). The platforms come in two versions, the CEVA XS-1100A optimized for wireless baseband applications, and the CEVA XS-1200A aimed at multimedia and other applications requiring high-performance signal processing. The platforms have already been licensed to two customers, including Mindspeed Technologies Inc., a leading supplier of semiconductor solutions for network infrastructure applications.
The platforms reduce development effort, the risk of costly silicon re-spins and, ultimately, time-to-market for embedded processor applications. It uses industry standard system buses, offering designers the ability to add their own hardware blocks or connect the DSP to other systems present on chip, making integrating CEVA cores a straightforward and efficient proposition. Both platforms support low power design requirements through CEVA's smart Power Management Unit (PMU) technology, which includes automatic sleep/wake of each resource and matrix separately according to transaction type, source, destination, initiator and duration.
The two platforms feature architecture enhancements that can lower die size and power consumption, without compromising on performance. They feature a complete AHB matrix, DMA, TDM ports, power management, external master and slave ports, complete lineup of DSP-oriented peripherals and interface to L2 memories.
Application-optimized Platforms
The CEVA XS1100A platform is optimized for wireless baseband and general purpose DSP solutions and tightly couples the CPU and DSP, which is required for real time baseband processing. It includes the following main features:
- Smart Power Management Unit (PMU) for dynamic control of power consumption
- Complete set of hardware peripherals extendible through an APB bridge
- Host controller connectivity through AHB compliant bridges
- Two-level memory architecture enabling shared memory between CEVA DSP and ARM cores, reducing system complexity, die size and power consumption
- Code replacement unit enabling on-the-fly firmware program bypasses
The CEVA XS1200A platform, aimed at multimedia and other DSP-intensive applications, enables a de-coupling of the CPU and DSP to support multiple independent clock systems. It integrates additional features that enhance the system processing power for applications such as digital multimedia devices and includes:
- A 16-channel advanced DMA with 3D transfer capabilities, allowing the DSP to handle most of the data traffic autonomously
- An interface to third-party accelerators that can be used for DSP-intensive applications
- Up to 4 TDM ports for use as the interface to audio and voice data
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