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Anaheim, California — Berkeley Design Automation, Inc., has introduced a SPICE accurate analog/RF mixed-signal verification based on co-simulation of its Analog FastSPICETM circuit simulator with Verilog HDL simulators.
Analog and RF design teams face increasingly difficult mixed-signal verification challenges. Complex blocks such as fractional-N PLLs, frequency synthesizers, and transmit and receive chains increasingly include complex digital logic. Nanometer CMOS ICs such as system-on-chips (SoCs), wireless transceivers, power ICs, and data converters have a rich mix of digital logic and high-performance analog/RF circuitry. Design teams need to verify their analog/RF circuitry with SPICE accuracy together with their digital logic using their standard Verilog simulator.
The Berkeley Design Automation tools include Analog FastSPICETM circuit simulation, Noise Analysis OptionTM device noise analyzer, RF FastSPICETM periodic analyzer, and PLL Noise AnalyzerTM stochastic nonlinear engine. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering higher performance and higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.
Analog FastSPICE Co-Simulation uses a standard Cadence Analog Design Environment based flow, includes mixed-analog/digital debugging, and integrates with Verilog simulators from Cadence NC-Verilog, Cadence Verilog-XL, and Mentor GraphicsModelSim. The Analog FastSPICE circuit simulator uses standard Cadence Spectre and Synopsys HSPICE netlists and models and delivers identical results to traditional "golden" SPICE simulators. The results are foundry certified down to 45nm.
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