|
Venice, Florida — Cadence Design Systems, Inc. today introduced C-to-Silicon Compiler, a high-level synthesis product supporting the creation and re-use of system-on-chip IP. The innovative technology in C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models — commonly used to verify, implement, and integrate SoCs — and system-level models, usually written in C/C++ and SystemC.
C-to-Silicon Compiler is the first product delivered from a new initiative codenamed Sydney and was developed within an internal incubation group headed by Michael McNamara, vice president/general manager, C-To-Silicon Compiler. The product aims are twofold: to bridge the gap between the use of C as a design language and RTL description of the design, and to improve the silicon implementation of the design by providing a direct link between manufacturing constraints and the C description.
The new product is not meant to compete with custom design projects, explains Ran Avinun, marketing group director, System Design and Verification, which must take advantage of specific optimizations available only with the use of existing tools and methods. By focusing just on IP meant for re-use, the new tool can provide good quality of results while saving the time required to optimize the design through the use of traditional Hardware Description Languages (HDL).
2. The flow and methodology enabled by C-to-Silicon Compiler.
Click here for a larger version
Figure 1 shows the flow and methodology enabled by C-to-Silicon Compiler. The Technology Library and Design Constraints are input separately from the source code of the design, enabling easier retargeting. The synthesis capability is provided by the Encounter RTL Compiler engine which is embedded in the tool. Mr. McNamara explained that the use of the proprietary Cadence synthesis engine does not prohibit engineers from taking the output of the new tool at the RTL format and use another third party synthesis tool to complete the production of a manufacturing ready design. In this way Cadence is not limiting the market of the new offering to just its own customers base, claims Mr. Avinun.
According to Mr. McNamara in addition to the capabilities already described, the new tool incorporates technology that enables parallel optimization of control and datapath logic, incremental synthesis for faster Engineering Change Order (ECO) handling, and generates Fast Hardware Models (FHM) that accelerate verification when the design team uses the Incisive Verification tool from Cadence. Although the FHM models are designed to meet the OSCI TLM 1.0 specification, and are scheduled to be updated to the just released 2.0 standard, they do also take advantage of Cadence's proprietary technology and are therefore, not usable with third party simulators.
For designers interested in verifying the equivalence of the C and RTL descriptions of the design, the new tool offers a direct integration with the SLEC product from Calypto.
The Cadence C-to-Silicon Compiler is available now in limited production. C-to-Silicon Compiler will be demonstrated during the DA SHOW/CDNLive! conference starting July 17.
See Also:
ESL handoff: closer than you think
Review Period for Draft Standard for TLM Closes Successfully
OSCI issues new TLM standard
|
