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PARIS — EDA companies Berkeley Design Automation Inc. and Solido Design Automation Inc. have validated a flow for rapid reduction in variation risk in nanometer designs at the transistor level.
Partners specified that Berkeley's Analog FastSpice (AFS) unified circuit verification platform is used as the simulation engine in Solido's Variation Designer. The result is variation analysis capabilities that enable designers to rapidly reduce variation risk.
Berkeley's AFS Platform is a unified circuit verification platform for analog, mixed-signal, and RF (AMS/RF) design teams. It is claimed to deliver SPICE accuracy, 5x-20x higher performance, >10M-element capacity, and advanced analyses.
Variation Designer, Solido (San Ramon, Calif.) noted, provides a scalable and extensible solution for solving problems created by process variation in nanometer designs at the transistor level.
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