Advanced probes, instrument take digital test console to full PCI Express 3.0 evaluation regime

Santa Clara, CA–Adding to the challenge of developing leading-edge interconnections is the frustration of testing them, whether in debug or verification/validation phase. The Agilent Technologies U4301A Digital Test Console supports PCI Express 3.0 (PCIe 3.0) speeds, up through PCIe 8 GT/s (Gen 3) with ×1 through ×16 support on both its protocol analyzer and link training sequencer state machine (LTSSM) exerciser.

Key to its ability to capture signals is the use of mid-bus and slot interposer probes using proprietary equalizing snoop probe (ESP) technology. The console provides stimulus, analysis, and debug capabilities under the impediments of maintaining equal electrical channel lengths, new encoding schemes, advanced protocols, and high speeds.

(Click on image to enlarge)
Using a PC-based controller to manage and interact with the system, you can capture raw data to examine low-level physical layer issues, and then perform analysis on the data and packets including context- and lane-sensitive perspectives. State-based triggering supports complex sequences as well as pattern- and error-based triggers. Dual phase-locked loops, one per direction, mean that the hardware can lock onto speed changes quickly and not miss data, which will be recorded in bidirectional 8+8 GB buffers, while basic LED indicators show lane status quickly.

All this would not be possible without basic, physical-level probes and associated circuitry that can capture signals yet not intrude. The ESP slot interposer probe is nearly invisible electrically, and adds mechanical stabilization to the DUT (device under test) mounting for consistency, The ESP mid-bus probe assembly adds micro pin-spring technology for reliable contact to the signal pads, and includes a spring-loaded cover to protect the delicate pins when not in use.

To fully evaluate the link, the LTSSM tests include sequences which check the complex and hard-to-test state transitions, and then provide detailed reports. The self-contained, self-powered PCIe Gen3 backplane for end-point testing eliminates the requirement for a motherboard, further simplifying setup and eliminating another potential source of problems.

Price and availability: The U4301A Digital Test Console has an average system price of $100,000, depending on specific configuration. It is available now.

For more information: contact Agilent Technologies Inc. http://www.agilent.com.♦

TECH PAPER
1. FPGA Design Methods for Fast Turn Around

TECH PAPER
2. Multi-Voltage Design Flow with Olympus-SoC

TECH PAPER
3. Realizing ESL with Scalable Transaction Level Models

TECH PAPER
4. How to Rapidly Create and Customize Compelling GUIs for Android-Based Devices