Cadence Design Systems, Inc., has released Cadence Encounter Digital Implementation (EDI) System 9.1, a complete and integrated digital design, implementation, and verification environment for the development of large-scale, complex SoCs.
The new and expanded suite of capabilities in EDI System 9.1 claims to answer the industry call for improved designer productivity in developing advanced low power and mixed signal SoCs at leading-edge process nodes - such as 32- and 28-nanometer - with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
Consumer demand for smaller, faster, feature-rich devices drives demand for larger-scale, higher-performance and lower-power SoCs. To compete in these markets, semiconductor companies must deliver the best and most differentiated designs, faster than the competition - a tricky combination that forces semiconductor companies to work through conflicting design objectives and sometimes incur higher manufacturing costs or take on greater technology and business risks.
EDI System 9.1 removes these challenges to design productivity through innovative design exploration capabilities. By combining automatic floorplan synthesis, data abstraction modeling, and new concurrent macro- and standard cell placement, all driven by fully the embedded signoff analysis capabilities of EDI System, users can quickly find and implement the optimal physical architecture of a chip.
Design exploration does this by automatically and concurrently examining thousands of combinations of design variables, option settings, floorplan architectures, and physical implementation approaches in parallel. This exhaustive examination allows users to fully explore the range of design possibilities, and deliver smaller, faster, higher functioning chips, while accelerating design schedules by weeks or months.
EDI System also improves designer productivity by broadening its integrated suite of native signoff capabilities. Building on its existing foundry certified power, timing, and signal integrity (SI) signoff capabilities, EDI System 9.1 now adds silicon-accurate extraction and design-for-manufacturing (DFM) analyses to complete the picture.
The new integrated, turbo QRC extraction capability provides fast in-design, incremental signoff extraction and drives fast and convergent design closure for physical and electrical design requirements. Also, since foundries now mandate DFM checks in the physical design flow at 40-nanometer and below, built-in, foundry-certified DFM analysis is a must-have at these nodes. The new integrated DFM capability - turbo Litho Physical Analyzer - brings built-in litho pattern intelligence and filtering to the interconnect routing phase, enabling automatic detection, prevention, and correction of potential litho hotspots before they happen. The capability improves DFM and yield for advanced 40-, 32- and 28-nanometer nodes and is faster than traditional lithography signoff tools.
EDI System 9.1 also extends its innovative memory architecture to achieve gains in memory capacity, acceleration in single-CPU operations, and improved performance scalability across its multi-CPU backplane, bringing efficient parallel processing throughout the design flow.
The convergence of design exploration, signoff-driven implementation, faster performance, and larger capacity in EDI System 9.1 has an impact to designer productivity. The software enables designers to design, implement, and verify chips 2-3X larger and 2X faster than traditional flows and with superior quality of silicon. The tight integration of signoff checks in the implementation phase enables exceptional correlation to final silicon, thereby reducing the potential for expensive silicon respins.
"Our 10GBASE-T PHYs are tuned for the highest performance and lowest power on the smallest die area," said Sridhar Begur, vice president of engineering at Teranetics. "With EDI System's end-to-end multi-CPU timing closure solution, we were able to reduce our turnaround time by more than half, and meet our design objectives significantly ahead of schedule. EDI System also provided us with an advanced 40-nanometer flow, enabling accurate, in-design prevention and fixing of lithography effects that translated to increased manufacturability and yield of our designs."
Datasheet:
Cadence Encounter Digital Implementation (EDI) System
