As the great physicist Niels Bohr once jokingly remarked, predictions are very difficult, especially with respect to the future. Although I am in no position to argue with a scientist of Bohr's caliber, I do think that some predictions are easier than others, especially if one has an insider's edge.
Therefore, at Verific Design Automation, we predict that 2005 will be the year where the electronic design automation (EDA) industry will see introductions of several SystemVerilog-based design tools.
In 2003, we noticed that many people were talking about SystemVerilog, especially EDA vendors Mentor Graphics and Synopsys, but there was very little market pull. It seemed the design community wasn't that interested (yet). This started to change in late 2003, when we got some indication from large semiconductor companies that they were seriously looking at SystemVerilog.
As a provider of VHDL and Verilog front-ends to the EDA market, we obviously were monitoring this closely. We also realized that we had an obligation here. Too often initiatives like these are on hold for years due to the chicken/egg effect. That is, designers aren't flocking to SystemVerilog because there are no EDA tools, and EDA vendors aren't investing in the development of a SystemVerilog front-end because there are no customers.
Verific Design Automation could make the difference here by taking the lead and develop a common front-end. Hence, we set out in 2004 and put significant resources into the development of a SystemVerilog parser, analyzer, and elaborator, which we license to EDA and semiconductor companies worldwide.
This has not been altogether easy. First, we needed to develop a comprehensive SystemVerilog test suite so we would have something against which to compare ourselves. We made sure that the test suite was developed independently from the software to prevent fault masking. Next came the issue of which version to support. After deciding to stick with SystemVerilog 3.1, we quickly found out that assertions (often referred to as SVA) were not very well defined in 3.1 and so we switched to 3.1a for SVA. While we were busy implementing fancy SystemVerilog constructs such as interfaces, we often scratched our heads about what the Language Reference Manual really intended to attain. But, in the end, we came up with the first version of a commercial and reusable parser, analyzer, and elaborator for SystemVerilog.
As a result of these efforts and our analysis of this market, we predict that the industry will see a variety of existing EDA tools supporting SystemVerilog 3.1 during the course of the year. Hardware description level (HDL) entry, logic synthesis, formal verification, simulation, emulation, simulation acceleration, and others can all draw from the existence of this common front-end. In the end, it is, of course, the end-user who really benefits. Not only does SystemVerilog become available sooner, but the front-ends from several EDA tools will actually be common. And for those of us who remember the early '90s, when every EDA tool had its own supported HDL subset, that may very well be biggest gain of all.
About the Author
Michiel Ligthart is Chief Operating Officer for Verific Design Automation in Alameda, CA. Prior to joining Verific, Ligthart was VP and GM of west-coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent 8 years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California, and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has an MSEE degree from Delft University of Technology, the Netherlands.
