In 2006, the much-anticipated move to 65-nanometer (nm) design will truly begin. By 2007 Gartner-Dataquest predicts that a considerable number of ASIC design starts will be in 65 nm or smaller process geometries. 2006, then, is the year in which designers will have to determine which design flow can best address the complex power and yield challenges associated with the 65-nm node, while enabling them to manage development cycles. The four key capabilities they'll need in an RTL-to-GDSII flow are precise power management and optimization, accurate yield analysis and optimization, higher levels of automation, and parallel processing.
The increasing performance and cell count requirements of 65-nm designs result in increased power. To minimize power consumption, the design flow must support techniques that minimize power while satisfying the timing requirement. For example, automatic MTCMOS switch insertion that enables certain domains in the design to be powered off, depending on the mode of operation, will be essential. Rather than fixing power problems after layout, static and dynamic power distribution and power dissipation issues must be addressed throughout the flow.
At 65-nm, the number and complexity of design rules is spiraling out of control, and employing these rules consumes huge amounts of memory and requires excessive run times. What's worse is that the rules often fail to capture the underlying physics, so even if designers adhere to all the rules the chips may still fail. To maximize yield and ensure manufacturability, the design flow will need to do more than design rule checks and resolution enhancement. Synthesis, placement, routing and analysis must be performed while taking into account yield issues. Of particular importance will be lithographic-aware placement that will be able to gauge the impact of recommended rules, such as adding redundant vias, on reliability and yield. For example, the system must be able to simultaneously consider the interdependent effects as the router is laying down a track: that track's parasitics must be extracted, delay calculations must be performed, the signal integrity of that route must be evaluated and the lithographic effects associated with the track on other structures must be determined.
Finding a flow that simply addresses the technical problems is not enough. Even though the design challenge is tougher, development cycles aren't getting any shorter. The only way to turn a profit in the semiconductor market at the 65-nm node is to accelerate the design flow. To do that, designers need a flow that provides higher levels of automation, tighter flow integration and faster runtimes. Such a flow will have to leverage parallel processing and be based on a unified data model where all of the tools—from synthesis to signal and power integrity and yield analysis, have immediate and concurrent access to exactly the same design data.
With so many new challenges and opportunities, there's no doubt that 2006 will mark the beginning of a new era in electronic design.
About the Author
Hamid Savoj co-founded Magma Design Automation and has served as senior vice president, product development since 2002. Before that he served as vice president, product development, and earlier as principal engineer. From 1994 to 1997 Savoj was a senior member of the consulting staff at Cadence Design Systems. Savoj received a doctorate degree in computer-aided design from the University of California, Berkeley.
