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What is a "roadmap"? In the technology world, a roadmap is a living document that projects contexts, requirements, and potential solutions into the future. Every industry roadmaps its key technologies, products and markets, for several basic reasons.
Roadmaps synchronize. For example, the International Technology Roadmap for Semiconductors (ITRS) is the means by which the semiconductor industry sets out trajectories of multiple semiconductor supplier industries (lithography, interconnect, test, assembly and packaging, design, etc.) to realize successive technology nodes (45nm, 32nm, 22nm, etc.). Synchronization reduces the risk of fatal delivery errors (solutions that are too little, too late, or too early) by industry players.
Roadmaps look ahead. For example, the 2001 ITRS told us that power and productivity imperatives would drive the industry to SOC design methodology convergence and a multicore-centric future, and that embedded software and the design-manufacturing interface presented looming crises. The implications of such predictions cannot be addressed by crash programs instituted only after wakeup calls; they demand proactive and sustained attention.
Roadmaps connect customers to their suppliers. Such a connection is typically one where "customer drives, supplier reacts" and operates at a more long-term horizon than the usual EDA "MRM" (management review meeting). The benefit here is reduced risk of another type of delivery error, namely, solutions that are plain wrong or mismatched to designer needs. Two anecdotes suggest that the long-term horizon is critical. (1) Having worked over the years with the Semiconductor Research Corporation and other entities to quantify worldwide EDA 'research funding gaps' vis-'-vis ITRS technology needs, I can say that there are really only around 6000 EDA R&D heads worldwide at any time. This number is at best stable (cf. industry revenues, research funding levels, etc.).
Some of these R&D resources are inevitably spent on fruitless directions, and are also subject to overlapping efforts (competitors build equivalent technologies, and geography (North America, Asia-Pacific, EU) creates triple-redundancy in funding of research programs). As the 6000 number includes professors and graduate students, this is clearly not a large resource; it must be as well-targeted as possible. (2) The wisdom at Intel and many other semiconductor companies is that around 6-7 years are needed to bring a new EDA technology "from DAC paper to production flow". Again, correct directions must be identified as early as possible.
Roadmaps implicitly establish the boundary between competitive and precompetitive. By this, I mean setting industry priorities, establishing agreements on non-differentiating ('commodity') infrastructure and standards, etc. The crises are piling up — software and concurrency, analog/RF, die-package-board and die stacking — and with a fixed number of EDA R&D engineers, we need to stop working on some issues. In the big picture, who wins a power format or current-source model or process variation model war is less critical to semiconductor industry health than consensus, interoperability, and moving on to fundamental design technology challenges.
So: Does the EDA industry have a roadmap?
Strictly speaking, yes, there are actually several EDA roadmaps. Within the semiconductor industry, the main EDA roadmap is found in the Design chapter of the ITRS, which provides quantified technology needs and potential solutions across system-level, logic- and physical-level, verification, DFT and DFM design technology arenas. The closely aligned ITRS System Drivers chapter roadmaps key product drivers and aligns with the iNEMI (International Electronics Manufacturing Initiative) roadmap. Working with many dedicated colleagues worldwide, I've chaired or co-chaired (with Dr. Juan-Antonio Carballo of IBM) the compilation of these chapters since 2000. There are other EDA roadmaps as well: Europe continually renews the MEDEA+ EDA roadmap, and Japan's STRJ Working Group 1 continually renews its roadmap for design technology. (The EDA Consortium created an "EDA 200X" roadmap around 1997-1998, but it has not been renewed since.)
But practically speaking, the answer is less clear. No EDA industry roadmap today provides all the "classic roadmap benefits" described above. And in a very pragmatic sense, whether the EDA industry has a roadmap is determined by EDA engineers ("Do you know your company's roadmap?"), EDA managers ("How much of your product roadmap and R&D budget is directed to solving long-term — i.e., more than 7 years — design technology needs?"), and EDA customers ("Do you proactively define (at what time horizon), or do you just accept and live with, the roadmaps of your EDA suppliers?"). Arguably, design technologists today do not have a roadmap — at least, not in the way that manufacturing technologists do.
Who is listening to any of the EDA roadmaps? While research consortia remain closely aware of the various EDA roadmaps and their implied research portfolios, there is in my view a growing disconnect with the EDA industry itself. For example, there is clearly less engagement of EDA industry CTOs and technologists in the ITRS Design roadmap effort today than there was 10 years ago. Many companies are in the throes of reinventing themselves; nearly all are focused on a 1-quarter horizon and not a 20-quarter horizon. Perhaps those MRMs with key customers and partners (Intel, TSMC, etc.) are a sufficient roadmapping process for EDA.
Is it even possible to roadmap EDA technology? Most other ITRS technologies have crisp metrics in terms of nanometers or picoamperes — but no clear "metric" exists for tool technologies that heuristically trade off solution quality for runtime in dealing with NP-hard optimizations.
Perhaps the question should be: Does the EDA industry need a roadmap? And at the coming Design Automation Conference (July 2009 in San Francisco), Dr. Juan-Antonio Carballo and I are organizing a small workshop to discuss exactly this question. Is it possible to roadmap EDA in a way that will be closely followed by the major industry players? Key constituencies (fabless, semi, consortia, etc.) will give their views. Juan-Antonio and I believe that the EDA industry will benefit from your engagement, and we look forward to your joining the discussion in July.
Andrew B. Kahng is Professor of CSE and ECE, UC San Diego
abk@ucsd.edu where his research focuses on integrated-circuit physical design and design for manufacturability. Kahng is general chair of the Design Automation Conference 2009.
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